The AES-ECB port entry point processed exactly one 16-byte block per
call, so a multi-block operation paid the cost of acquiring the
peripheral, enabling its clock and writing the key once per block. That
fixed cost is ~13.7 us on ESP32-C6 and dominates the AES transform
itself at this scale.
Add esp_aes_crypt_ecb_blocks(), which submits an entire buffer in a
single hardware operation, mirroring the structure of
esp_aes_crypt_cbc(). esp_aes_crypt_ecb() becomes a thin wrapper over it
with length = 16 and is unchanged behaviourally; the public API is
unchanged.
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.
The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.
This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
- Fix incorrect setting in the edge interrupt acknowledgement API
- Avoid executing the service call dispatcher in the U-mode ecall,
rather execute `mret` to jump it
- Avoid `t1` register corruption when processing `ecall`
- Switch back to the bootloader stack from TEE stack after the
execution of the entire TEE initialization routine
- Remove `mret` for jumping to the service call dispatcher; instead, enable
interrupts and execute directly
- Fix potential corruption of the `t3` register when returning from a service
call
- Simplify the secure service dispatcher function
Pranav Sonawane
Laukik Hase
Xiao Xufeng
harshal.patil
Mahavir Jain
Sachin Billore