Merges https://github.com/espressif/esp-idf/pull/19047
The engine's "idle" state was a binary semaphore that the completion ISR
gave only AFTER leaving the engine spinlock, while ppa_do_operation
inserted its transaction under that spinlock and then tried the semaphore
with a zero timeout. On the ISR's own core the two cannot interleave. When
the submitting task runs on the OTHER core it can insert between the
ISR's "queue empty" decision and its give, find the semaphore still taken,
assume the ISR will chain-start the transaction, and be left at the head of
an idle engine's queue. It only starts when a later submission's completion
picks it up; a lone last submission never completes and a caller waiting on
its done callback blocks forever.
Seen on ESP32-P4 with the PPA/2D-DMA interrupt on core 0 and SRM
transactions submitted from a core-1 task: ~130 stranded transactions per
20000 when single transactions are submitted at their own duration, none
when the submitter is on core 0; none after this change.
Replace the semaphore with a `busy` flag that both sides read and write
only under the engine spinlock: the submitter inserts and, if the engine
is idle, marks it busy and starts the transaction itself; the ISR clears
the flag in the same critical section in which it finds the queue empty.
Blocking mode also clears a stale give on the recycled per-transaction
semaphore (the ISR gives it unconditionally, non-blocking callers never
take it), which made a blocking operation return before its transaction
had finished.
Objects with atomic members must not be allocated to PSRAM, otherwise
the ordering guarantee of atomic accesses is weakened due to a hardware
behavior on ESP32 chips. Explicitly request MALLOC_CAP_INTERNAL |
MALLOC_CAP_8BIT for:
- i2c master bus object (atomic status/trans_idx)
- i3c master bus object (atomic fsm)
- ISP processor and AE/AF/AWB/HIST controllers (atomic fsm)
- JPEG decoder/encoder dma2d transaction descriptors (atomic started)
- PPA transaction storage embedding dma2d_trans_t
- dma2d m2m test transaction embedding dma2d_trans_t
PPA SRM engine added YUV422 and GRAY8 color mode support
PPA SRM engine macro block size increased to 32x32
PPA Blending engine added YUV420, YUV422 and GRAY8 color mode support
1. The smallest scale size can be 1/16, not 1/15
2. Fix potential heap corruption if scale to a smaller size (OOB)
3. Fix mismatching writeback and invalidate data size if in_bg/fg_buffer and out_buffer
are the same one and L2 cacheline size is larger than L1 cacheline size
Add burst_length option to client
Change uint32_t to color_pixel_rgb888_data_t
Descriptor always malloc with MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT
Add dscr-port mode block size configuration as a separate API in 2D-DMA driver
Do writeback only on an extended window, instead of entire picture
Remove the check for in_accepting_trans_state
Add color_pixel_xxxx_data_t structures to color_types.h
Fix PM lock protection (Tested, now works well)
* CPU_MAX, PM lock and semaphore order
* Remove ppa_driver PM lock
Modify concurrency (queue, trans recycle, semaphore, ...)
Add programming guide
Add test apps
Modified API operation configuration structure
Rename invoker to client
Support YUV420 color mode for SRM
Move PPA srm/blending engine reset ahead of any 2D-DMA channel configurations
Added doxygen
Refactored driver to malloc trans_elm memory when registering the client
Cleaned up driver
Added API check
One client now only responsible for one operation
Song Ruo Jing
Matt Sephton
morris
Chen Jichang
Marius Vikhammer
Alexey Lapshin