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Merge branch 'fix/for_cache_after_p4_wb_loss_issue' into 'master'

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fix(esp_rom): avoid critical issue in writeback

See merge request espressif/esp-idf!48498
This commit is contained in:
Jiang Jiang Jian
2026-05-21 22:10:00 +08:00
parent c1b7f38212 c7032e78aa
commit fff1564266
23 changed files with 289 additions and 29 deletions
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components/esp_rom/esp32s31/Kconfig.soc_caps.in
+4
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@@ -94,3 +94,7 @@ config ESP_ROM_PRINTS_LOCKUP_STATUS
config ESP_ROM_BOOTLOADER_OFFSET_FLASH
hex
default 0x2000
config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP
bool
default y
components/esp_rom/esp32s31/esp_rom_caps.h
+1
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@@ -30,3 +30,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_PRINTS_LOCKUP_STATUS (1) // ROM bootloader already prints CPU lockup diagnostic status
#define ESP_ROM_BOOTLOADER_OFFSET_FLASH (0x2000) // Bootloader offset in flash determined by the ROM bootloader
#define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, need map parameter
components/esp_rom/esp32s31/include/esp32s31/rom/cache.h
+1
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@@ -163,6 +163,7 @@ typedef enum {
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE)
#define CACHE_MAP_DCACHE_MASK (CACHE_MAP_L1_DCACHE)
struct cache_internal_stub_table {
uint32_t (*l1_icache_line_size)(void);
components/esp_rom/esp32s31/ld/esp32s31.rom.ld
+4 -4
View File
@@ -213,12 +213,12 @@ ROM_Boot_Cache_Init = 0x2f8005e0;
Cache_Sync_Addr = 0x2f8005e4;
Cache_Invalidate_Addr = 0x2f8005e8;
Cache_Clean_Addr = 0x2f8005ec;
Cache_WriteBack_Addr = 0x2f8005f0;
Cache_WriteBack_Invalidate_Addr = 0x2f8005f4;
PROVIDE( Cache_WriteBack_Addr = 0x2f8005f0 );
PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x2f8005f4 );
Cache_Invalidate_All = 0x2f8005f8;
Cache_Clean_All = 0x2f8005fc;
Cache_WriteBack_All = 0x2f800600;
Cache_WriteBack_Invalidate_All = 0x2f800604;
PROVIDE( Cache_WriteBack_All = 0x2f800600 );
PROVIDE( Cache_WriteBack_Invalidate_All = 0x2f800604 );
Cache_Mask_All = 0x2f800608;
Cache_Suspend_L1_CORE0_ICache_Autoload = 0x2f80060c;
Cache_Resume_L1_CORE0_ICache_Autoload = 0x2f800610;