Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'fix/for_cache_after_p4_wb_loss_issue' into 'master'

Browse Source 
fix(esp_rom): avoid critical issue in writeback

See merge request espressif/esp-idf!48498
This commit is contained in:
Jiang Jiang Jian
2026-05-21 22:10:00 +08:00
parent c1b7f38212 c7032e78aa
commit fff1564266
23 changed files with 289 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_rom/esp32h4/Kconfig.soc_caps.in
+4
View File
@@ -74,3 +74,7 @@ config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
config ESP_ROM_BOOTLOADER_OFFSET_FLASH
hex
default 0x2000
config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP
bool
default y
components/esp_rom/esp32h4/esp_rom_caps.h
+1
View File
@@ -24,3 +24,4 @@
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
#define ESP_ROM_BOOTLOADER_OFFSET_FLASH (0x2000) // Bootloader offset in flash determined by the ROM bootloader
#define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, no map parameter
components/esp_rom/esp32h4/ld/esp32h4.rom.ld
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -182,12 +182,12 @@ Cache_Sync_Items = 0x400005b8;
Cache_Op_Addr = 0x400005bc;
Cache_Invalidate_Addr = 0x400005c0;
Cache_Clean_Addr = 0x400005c4;
Cache_WriteBack_Addr = 0x400005c8;
Cache_WriteBack_Invalidate_Addr = 0x400005cc;
PROVIDE( Cache_WriteBack_Addr = 0x400005c8 );
PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x400005cc );
Cache_Invalidate_All = 0x400005d0;
Cache_Clean_All = 0x400005d4;
Cache_WriteBack_All = 0x400005d8;
Cache_WriteBack_Invalidate_All = 0x400005dc;
PROVIDE( Cache_WriteBack_All = 0x400005d8 );
PROVIDE( Cache_WriteBack_Invalidate_All = 0x400005dc );
Cache_Mask_All = 0x400005e0;
Cache_UnMask_Dram0 = 0x400005e4;
Cache_Suspend_Autoload = 0x400005e8;