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Merge branch 'fix/p4_fixed_mdc_config_v6.0' into 'release/v6.0'

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fix(esp_eth): fixed ESP32P4 CSR clock range used to determine MDC (v6.0)

See merge request espressif/esp-idf!44224
This commit is contained in:
Jiang Jiang Jian
2025-12-21 15:19:34 +08:00
parent 4ccd8f99b6 20a004f141
commit ff9d18afea
10 changed files with 72 additions and 4 deletions
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components/hal/esp32/include/hal/emac_ll.h
+7
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@@ -22,6 +22,7 @@
#include "soc/emac_mac_struct.h"
#include "soc/emac_ext_struct.h"
#include "soc/dport_reg.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
@@ -746,6 +747,12 @@ static inline void emac_ll_pause_frame_enable(emac_ext_dev_t *ext_regs, bool ena
}
/*************** End of ext regs operation *********************/
static inline soc_module_clk_t emac_ll_get_csr_clk_src(void)
{
// Source of the ESP32 EMAC CRS clock is APB clock.
return SOC_MOD_CLK_APB;
}
#ifdef __cplusplus
}
#endif