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Merge branch 'fix/p4_fixed_mdc_config_v6.0' into 'release/v6.0'

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fix(esp_eth): fixed ESP32P4 CSR clock range used to determine MDC (v6.0)

See merge request espressif/esp-idf!44224
This commit is contained in:
Jiang Jiang Jian
2025-12-21 15:19:34 +08:00
parent 4ccd8f99b6 20a004f141
commit ff9d18afea
10 changed files with 72 additions and 4 deletions
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components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+7
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@@ -8,6 +8,7 @@
#include "esp_clk_tree.h"
#include "esp_err.h"
#include "esp_check.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "hal/clk_gate_ll.h"
#include "hal/clk_tree_hal.h"
@@ -32,6 +33,12 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
case SOC_MOD_CLK_XTAL:
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
break;
case SOC_MOD_CLK_SYS:
clk_src_freq = clk_hal_sys_get_freq_hz();
break;
case SOC_MOD_CLK_APB:
clk_src_freq = clk_hal_apb_get_freq_hz();
break;
case SOC_MOD_CLK_PLL_F20M:
clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ / clk_ll_pll_f20m_get_divider() * MHZ;
break;