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docs(system): update API references for H4 and S31

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Add target-specific power-management frequencies and capability
conditions so later chips do not need chip-by-chip list updates.
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Marius Vikhammer
2026-09-11 09:55:47 +08:00
parent 27506a49bc
commit ff41b52fc6
25 changed files with 176 additions and 45 deletions
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docs/en/api-reference/system/freertos_idf.rst
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@@ -47,7 +47,7 @@ Although an SMP system allows threads to switch cores, there are scenarios where
SMP on an ESP Target
^^^^^^^^^^^^^^^^^^^^
ESP targets such as ESP32, ESP32-S3, ESP32-P4 and ESP32-H4 are dual-core SMP SoCs. These targets have the following hardware features that make them SMP-capable:
ESP targets with dual HP cores have the following hardware features that make them SMP-capable:
- Two identical cores are known as Core 0 and Core 1. This means that the execution of a piece of code is identical regardless of which core it runs on.
- Symmetric memory (with some small exceptions).