From fe18ed97dd9048412a8f0601b9ec17227d89988f Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Tue, 9 Jun 2026 14:54:30 +0530 Subject: [PATCH] feat: added call to aquire clock source for H4 and H21 AES crypto --- components/esp_rom/esp32h4/include/esp32h4/rom/hmac.h | 2 -- components/esp_security/src/esp32h21/esp_crypto_clk.h | 3 ++- components/esp_security/src/esp32h4/esp_crypto_clk.h | 3 ++- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/components/esp_rom/esp32h4/include/esp32h4/rom/hmac.h b/components/esp_rom/esp32h4/include/esp32h4/rom/hmac.h index 174197277eb..5ae1ff0942c 100644 --- a/components/esp_rom/esp32h4/include/esp32h4/rom/hmac.h +++ b/components/esp_rom/esp32h4/include/esp32h4/rom/hmac.h @@ -11,8 +11,6 @@ extern "C" { #endif -//TODO: [ESP32H4] IDF-12257 inherit from verification branch, need check - #include #include #include "efuse.h" diff --git a/components/esp_security/src/esp32h21/esp_crypto_clk.h b/components/esp_security/src/esp32h21/esp_crypto_clk.h index 79c490ff53b..14865e0f7c7 100644 --- a/components/esp_security/src/esp32h21/esp_crypto_clk.h +++ b/components/esp_security/src/esp32h21/esp_crypto_clk.h @@ -6,6 +6,7 @@ #include "soc/soc.h" #include "soc/pcr_reg.h" +#include "esp_private/esp_clk_tree_common.h" #pragma once @@ -16,6 +17,6 @@ void esp_crypto_common_clk_enable(bool enable); static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 96M PLL clock + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, true); REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); - // TODO: IDF-12266 need to call esp_clk_tree_enable_src() to acquire PLL 96M clock gating } diff --git a/components/esp_security/src/esp32h4/esp_crypto_clk.h b/components/esp_security/src/esp32h4/esp_crypto_clk.h index 26f66ddacdd..cf0a043509f 100644 --- a/components/esp_security/src/esp32h4/esp_crypto_clk.h +++ b/components/esp_security/src/esp32h4/esp_crypto_clk.h @@ -6,6 +6,7 @@ #include "soc/soc.h" #include "soc/pcr_reg.h" +#include "esp_private/esp_clk_tree_common.h" #pragma once @@ -16,6 +17,6 @@ void esp_crypto_common_clk_enable(bool enable); static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 96M PLL clock + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, true); REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); - // TODO: IDF-12266 need to call esp_clk_tree_enable_src() to acquire PLL 96M clock gating }