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Merge branch 'feat/support_esp32p4_rev3.1_lowpower_v5.5' into 'release/v5.5'

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feat: esp32p4 eco6 lowpower support and leakage optimization (v5.5)

See merge request espressif/esp-idf!45532
This commit is contained in:
Jiang Jiang Jian
2026-03-06 19:54:06 +08:00
parent 711c3956f9 1187afe516
commit fdfcae24e3
8 changed files with 230 additions and 40 deletions
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components/esp_hw_support/sleep_modes.c
+13 -6
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@@ -126,6 +126,10 @@
#include "hal/gpio_ll.h"
#endif
#if SOC_MSPI_HAS_INDEPENT_IOMUX
#include "hal/mspi_ll.h"
#endif
#if SOC_PM_SUPPORT_PMU_CLK_ICG
#include "soc/pmu_icg_mapping.h"
#endif
@@ -920,6 +924,9 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
if(!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & PMU_SLEEP_PD_TOP)) {
#if SOC_MSPI_HAS_INDEPENT_IOMUX
mspi_ll_hold_all_flash_pins();
#else // !SOC_MSPI_HAS_INDEPENT_IOMUX
#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
/* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */
gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS0);
@@ -928,16 +935,14 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
/* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */
gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS1);
#endif
#endif // !SOC_MSPI_HAS_INDEPENT_IOMUX
}
#endif
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
if (sleep_flags & PMU_SLEEP_PD_TOP) {
#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
sleep_retention_do_extra_retention(true);
#endif
}
#endif
#endif // CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#if SOC_PMU_SUPPORTED
#if SOC_PM_CPU_RETENTION_BY_SW && ESP_SLEEP_POWER_DOWN_CPU
@@ -968,17 +973,19 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
sleep_retention_do_extra_retention(false);
#endif
}
#endif
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
/* Unhold the SPI CS pin */
if(!(sleep_flags & RTC_SLEEP_PD_VDDSDIO) && (sleep_flags & PMU_SLEEP_PD_TOP)) {
#if SOC_MSPI_HAS_INDEPENT_IOMUX
mspi_ll_unhold_all_flash_pins();
#else // !SOC_MSPI_HAS_INDEPENT_IOMUX
#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS0);
#endif
#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS1);
#endif
#endif // !SOC_MSPI_HAS_INDEPENT_IOMUX
}
#endif
/* Cache Resume 1: Resume cache for continue running*/