mirror of
https://github.com/espressif/esp-idf.git
synced 2026-05-28 16:46:31 +03:00
Merge branch 'feat/update_efuse_doc_for_new_chips' into 'master'
feat(docs): Update efuse doc for H4 and H21 Closes IDF-12959 and IDF-12154 See merge request espressif/esp-idf!48706
This commit is contained in:
@@ -121,11 +121,7 @@ api-reference/system/random.rst
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api-reference/system/esp_https_ota.rst
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api-reference/system/sleep_modes.rst
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api-reference/system/ota.rst
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api-reference/system/efuse.rst
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api-reference/system/inc/power_management_esp32h21.rst
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api-reference/system/inc/show-efuse-table_ESP32-H21.rst
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api-reference/system/inc/espefuse_summary_ESP32-H21.rst
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api-reference/system/inc/espefuse_summary_ESP32-H21_dump.rst
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api-reference/system/power_management.rst
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security/vulnerabilities.rst
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security/tee/index.rst
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@@ -129,11 +129,7 @@ api-reference/system/mm.rst
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api-reference/system/esp_https_ota.rst
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api-reference/system/sleep_modes.rst
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api-reference/system/ota.rst
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api-reference/system/efuse.rst
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api-reference/system/inc/power_management_esp32h4.rst
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api-reference/system/inc/show-efuse-table_ESP32-H4.rst
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api-reference/system/inc/espefuse_summary_ESP32-H4.rst
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api-reference/system/inc/espefuse_summary_ESP32-H4_dump.rst
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api-reference/system/power_management.rst
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security/index.rst
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security/flash-encryption.rst
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@@ -75,7 +75,7 @@ Record Format
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In simple cases, each record occupies a single row in the table. Each record contains the following values (i.e., columns):
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{IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3", esp32c2 = "EFUSE_BLK3"}
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{IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3", esp32c2 = "EFUSE_BLK3", esp32s31 = "EFUSE_BLK9"}
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.. code-block:: none
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@@ -1,3 +1,164 @@
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.. code-block:: none
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To be updated
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idf.py -p PORT efuse-summary
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Executing action: efuse-summary
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(...)
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=== Run "summary" command ===
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EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
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----------------------------------------------------------------------------------------
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Config fuses:
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WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000)
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RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
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DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0)
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1: disabled. 0: enabled
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POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is = False R/W (0b0)
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enabled. 1: enabled. 0: disabled
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DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or = False R/W (0b0)
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enabled. 1: disabled. 0: enabled
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RPT4_RESERVED0_2 (BLOCK0) Reserved = 0 R/W (0b00)
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RPT4_RESERVED0_1 (BLOCK0) Reserved = False R/W (0b0)
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DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
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enabled. 1: disabled. 0: enabled
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UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00)
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HYS_EN_PAD0 (BLOCK0) Set bits to enable hysteresis function of PAD0~5 = 0 R/W (0b000000)
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HYS_EN_PAD1 (BLOCK0) Set bits to enable hysteresis function of PAD6~27 = 0 R/W (0b0000000000000000000000)
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RXIQ_0 (BLOCK1) Stores RF Calibration data. RXIQ data 0 = 0 R/W (0b0000000)
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RXIQ_1 (BLOCK1) Stores RF Calibration data. RXIQ data 1 = 0 R/W (0b0000000)
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BLOCK_USR_DATA (BLOCK3) User data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved)
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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Flash fuses:
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FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0)
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in unit of ms. When the value less than 15; the
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waiting time is the programmed value. Otherwise; the
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waiting time is 2 times the programmed value
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FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a = False R/W (0b0)
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resume command during SPI boot. 1: forced. 0:not
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forced
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FLASH_CAP (BLOCK1) Stores the flash cap = 0 R/W (0b000)
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FLASH_TEMP (BLOCK1) Stores the flash temp = 0 R/W (0b00)
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FLASH_VENDOR (BLOCK1) Stores the flash vendor = 0 R/W (0b000)
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Identity fuses:
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RXIQ_VERSION (BLOCK1) Stores RF Calibration data. RXIQ version = 0 R/W (0b000)
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WAFER_VERSION_MINOR (BLOCK1) Stores the wafer version minor = 0 R/W (0b000)
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WAFER_VERSION_MAJOR (BLOCK1) Stores the wafer version major = 0 R/W (0b00)
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DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0)
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PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000)
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OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration = 0 R/W (0b000)
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data in BLOCK1
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BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00)
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DISABLE_BLK_VERSION_MAJOR (BLOCK2) Disables check of blk version major = False R/W (0b0)
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Jtag fuses:
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JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between = False R/W (0b0)
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usb_to_jtag and pad_to_jtag through strapping
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gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are
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equal to 0
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SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. = 0 R/W (0b000)
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Odd number: disabled. Even number: enabled
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DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the = False R/W (0b0)
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hard way(permanently). 1: disabled. 0: enabled
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Mac fuses:
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MAC (BLOCK1) MAC address
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= 00:00:00:00:00:00 (OK) R/W
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MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W
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CUSTOM_MAC (BLOCK3) Custom MAC
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= 00:00:00:00:00:00 (OK) R/W
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MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M
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= 00:00:00:00:00:00:00:00 (OK) R/W
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AC_EXT[1]:MAC[3]:MAC[4]:MAC[5]
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Security fuses:
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DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip = False R/W (0b0)
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into download mode is disabled or enabled. 1:
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disabled. 0: enabled
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SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during = False R/W (0b0)
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boot_mode_download is disabled or enabled. 1: disabled. 0:
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enabled
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DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is = False R/W (0b0)
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disabled or enabled(except in SPI boot mode). 1:
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disabled. 0: enabled
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SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
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and disables otherwise
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SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0)
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SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0)
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SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0)
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KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0)
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KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0)
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KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0)
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KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0)
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KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0)
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KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0)
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SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00)
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clock random divide mode
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ECDSA_FORCE_USE_HARDWARE_K (BLOCK0) Represents whether hardware random number k is = False R/W (0b0)
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forced used in ESDCA. 1: force used. 0: not force
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used
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CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. = False R/W (0b0)
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1:enabled. 0: disabled
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SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or = False R/W (0b0)
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disabled. 1: enabled. 0: disabled
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SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0)
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is enabled or disabled. 1: enabled. 0: disabled
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DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or = False R/W (0b0)
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enabled. 1: disabled. 0: enabled
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ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0)
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disabled. 1: enabled. 0: disabled
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SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF = 0 R/W (0x0000)
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anti-rollback feature
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SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0)
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or enabled when Secure Boot is enabled. 1:
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disabled. 0: enabled
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BLOCK_KEY0 (BLOCK4)
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Purpose: USER
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Key0 or user data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLOCK_KEY1 (BLOCK5)
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Purpose: USER
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Key1 or user data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLOCK_KEY2 (BLOCK6)
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Purpose: USER
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Key2 or user data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLOCK_KEY3 (BLOCK7)
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Purpose: USER
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Key3 or user data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLOCK_KEY4 (BLOCK8)
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Purpose: USER
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Key4 or user data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLOCK_KEY5 (BLOCK9)
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Purpose: USER
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Key5 or user data
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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Usb fuses:
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DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to = False R/W (0b0)
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jtag is disabled or enabled. 1: disabled. 0:
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enabled
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USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0)
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1: exchanged. 0: not exchanged
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DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Set this bit to disable USB-Serial-JTAG print = False R/W (0b0)
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during rom boot
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DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download = False R/W (0b0)
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function is disabled or enabled. 1: disabled. 0:
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enabled
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Vdd fuses:
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VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as = False R/W (0b0)
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gpio. 1: functioned. 0: not functioned
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Wdt fuses:
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WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00)
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is selected at startup. 1: selected. 0: not
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selected
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@@ -1,3 +1,21 @@
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.. code-block:: none
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To be updated
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idf.py -p PORT efuse-dump
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Executing action: efuse-dump
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Running espefuse in directory <project-directory>
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Executing "espefuse dump --chip esp32h21"...
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espefuse v5.3.dev3
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Connecting....
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=== Run "dump" command ===
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BLOCK0 ( ) [0 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000
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MAC_SPI_8M_0 (BLOCK1 ) [1 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_SYS_DATA (BLOCK2 ) [2 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_USR_DATA (BLOCK3 ) [3 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_KEY0 (BLOCK4 ) [4 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_KEY1 (BLOCK5 ) [5 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_KEY2 (BLOCK6 ) [6 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_KEY3 (BLOCK7 ) [7 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_KEY4 (BLOCK8 ) [8 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_KEY5 (BLOCK9 ) [9 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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BLOCK_SYS_DATA2 (BLOCK10 ) [10] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
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@@ -1,3 +1,248 @@
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.. code-block:: none
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To be updated
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idf.py -p PORT efuse-summary
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Executing action: efuse-summary
|
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(...)
|
||||
|
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=== Run "summary" command ===
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EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
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----------------------------------------------------------------------------------------
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Config fuses:
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WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000)
|
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RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
|
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DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0)
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abled. 1: disabled 0: enabled
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PVT_GLITCH_EN (BLOCK0) Represents whether to enable PVT power glitch moni = False R/W (0b0)
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tor function.1:Enable. 0:Disable
|
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PVT_GLITCH_MODE (BLOCK0) Use to configure glitch mode = 0 R/W (0b00)
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DIS_CORE1 (BLOCK0) Represents whether the CPU-Core1 is disabled. 1: = False R/W (0b0)
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Disabled. 0: Not disable
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ECC_FORCE_CONST_TIME (BLOCK0) Represents whether to force ecc to use const-time = False R/W (0b0)
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calculation mode. 1: Enable. 0: Disable
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KM_DISABLE_DEPLOY_MODE (BLOCK0) Represents whether the new key deployment of key m = 0 R/W (0b00000)
|
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anager is disabled. Bit0: Represents whether the n
|
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ew ECDSA key deployment is disabled0: Enabled1: Di
|
||||
sabledBit1: Represents whether the new XTS-AES (fl
|
||||
ash and PSRAM) key deployment is disabled0: Enable
|
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d1: DisabledBit2: Represents whether the new HMAC
|
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key deployment is disabled0: Enabled1: DisabledBit
|
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3: Represents whether the new DS key deployment is
|
||||
disabled0: Enabled1: Disabled
|
||||
KM_RND_SWITCH_CYCLE (BLOCK0) Represents the cycle at which the Key Manager swit = 0 R/W (0b00)
|
||||
ches random numbers.0: Controlled by the \hyperref
|
||||
[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWIT
|
||||
CH\_CYCLE} register. For more information; please
|
||||
refer to Chapter \ref{mod:keymng} \textit{\nameref
|
||||
{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Ke
|
||||
y Manager clock cycles3: 32 Key Manager clock cycl
|
||||
es
|
||||
KM_DEPLOY_ONLY_ONCE (BLOCK0) Represents whether the corresponding key can be de = 0 R/W (0b00000)
|
||||
ployed only once.Bit0: Represents whether the ECDS
|
||||
A key can be deployed only once0: The key can be d
|
||||
eployed multiple times1: The key can be deployed o
|
||||
nly onceBit1: Represents whether the XTS-AES (flas
|
||||
h and PSRAM) key can be deployed only once0: The k
|
||||
ey can be deployed multiple times1: The key can be
|
||||
deployed only onceBit2: Represents whether the HM
|
||||
AC key can be deployed only once0: The key can be
|
||||
deployed multiple times1: The key can be deployed
|
||||
only onceBit3: Represents whether the DS key can b
|
||||
e deployed only once0: The key can be deployed
|
||||
multiple times1: The key can be deployed only once
|
||||
DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
|
||||
enabled. 1: disabled 0: enabled
|
||||
UART_PRINT_CONTROL (BLOCK0) Represents the type of UART printing. 00: force en = 0 R/W (0b00)
|
||||
able printing 01: enable printing when GPIO8 is re
|
||||
set at low level 10: enable printing when GPIO8 is
|
||||
reset at high level 11: force disable printing
|
||||
HUK_GEN_STATE (BLOCK0) Represents whether the HUK generate mode is valid. = 0 R/W (0b00000)
|
||||
Odd count of bits with a value of 1: InvalidEven c
|
||||
ount of bits with a value of 1: Valid
|
||||
DCDC_CCM_EN (BLOCK0) Represents whether change DCDC to CCM mode = False R/W (0b0)
|
||||
PVT_LIMIT (BLOCK1) Power glitch monitor threthold = 0 R/W (0x0000)
|
||||
PVT_CELL_SELECT (BLOCK1) Power glitch monitor PVT cell select = 0 R/W (0b0000000)
|
||||
PVT_PUMP_LIMIT (BLOCK1) Use to configure voltage monitor limit for charge = 0 R/W (0x00)
|
||||
pump
|
||||
PUMP_DRV (BLOCK1) Use to configure charge pump voltage gain = 0 R/W (0x0)
|
||||
HYS_EN_PAD (BLOCK1) Represents whether the hysteresis function of = False R/W (0b0)
|
||||
corresponding PAD is enabled. 1: enabled 0:disabled
|
||||
PVT_GLITCH_CHARGE_RESET (BLOCK1) Represents whether to trigger reset or charge pump = False R/W (0b0)
|
||||
when PVT power glitch happened.1:Trigger charge p
|
||||
ump. 0:Trigger reset
|
||||
PSRAM_CAP (BLOCK1) Psram capacity = 0 R/W (0b000)
|
||||
PSRAM_VENDOR (BLOCK1) Psram vendor = 0 R/W (0b00)
|
||||
TEMP (BLOCK1) Temp (die embedded inside) = 0 R/W (0b00)
|
||||
ADJUST_1V2 (BLOCK1) SPI LDO adjust of 1.2v = 0 R/W (0x0)
|
||||
ADJUST_1V8 (BLOCK1) SPI LDO adjust of 1.8v = 0 R/W (0x0)
|
||||
ACTIVE_DCDC_1V25 (BLOCK1) DCDC-DCDC DBIAS of 1.25v = 0 R/W (0x0)
|
||||
ACTIVE_DCDC_1V35 (BLOCK1) DCDC-DCDC DBIAS of 1.35v = 0 R/W (0x0)
|
||||
SLP_DCDC (BLOCK1) DCDC DBIAS in sleep = 0 R/W (0b00000)
|
||||
VDD_3V4_DOUT (BLOCK2) ADC dout of vdd 3.4v = 0 R/W (0b0000000000)
|
||||
INITCODE_DIFF_1P8_3P3 (BLOCK2) Initcode diff between IO LDO 1.8v and 3.3v = 0 R/W (0b00000)
|
||||
HI_DOUT_DIFF_1P8_3P3 (BLOCK2) HI dout diff between IO LDO 1.8v and 3.3v = 0 R/W (0b00000)
|
||||
BLOCK_USR_DATA (BLOCK3) User data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved)
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Flash fuses:
|
||||
FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0b000)
|
||||
in unit of ms. When the value less than 15; the wa
|
||||
iting time is the programmed value. Otherwise; the
|
||||
waiting time is 2 times the programmed value
|
||||
FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0)
|
||||
sume command during SPI boot. 1: forced 0:not forc
|
||||
ed
|
||||
FLASH_LDO_EFUSE_SEL (BLOCK0) Represents whether to select efuse control flash l = False R/W (0b0)
|
||||
do default voltage. 1 : efuse 0 : strapping
|
||||
FLASH_LDO_POWER_SEL (BLOCK1) Represents which flash ldo be select: 1: FLASH LDO = False R/W (0b0)
|
||||
1P2 0 : FLASH LDO 1P8
|
||||
FLASH_CAP (BLOCK1) Flash capacity = 0 R/W (0b000)
|
||||
FLASH_VENDOR (BLOCK1) Flash vendor = 0 R/W (0b000)
|
||||
|
||||
Identity fuses:
|
||||
WAFER_VERSION_MINOR (BLOCK1) Minor chip version = 1 R/W (0x1)
|
||||
WAFER_VERSION_MAJOR (BLOCK1) Major chip version = 0 R/W (0b00)
|
||||
DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0)
|
||||
DISABLE_BLK_VERSION_MAJOR (BLOCK1) Disables check of blk version major = False R/W (0b0)
|
||||
BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000)
|
||||
BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00)
|
||||
PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000)
|
||||
OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Jtag fuses:
|
||||
JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0)
|
||||
ag and pad_to_jtag through strapping gpio15 when b
|
||||
oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are
|
||||
equal to 0 is enabled or disabled. 1: enabled 0: d
|
||||
isabled
|
||||
DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0)
|
||||
y(permanently). 1: disabled 0: enabled
|
||||
SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000)
|
||||
dd number: disabled Even number: enabled
|
||||
|
||||
Mac fuses:
|
||||
MAC (BLOCK1) MAC address
|
||||
= 30:ed:a0:ed:57:cc (OK) R/W
|
||||
MAC_EXT (BLOCK1) Represents the extended bits of MAC address = 00:00 (OK) R/W
|
||||
CUSTOM_MAC (BLOCK3) Custom MAC
|
||||
= 00:00:00:00:00:00 (OK) R/W
|
||||
MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M
|
||||
= 30:ed:a0:00:00:ed:57:cc (OK) R/W
|
||||
AC_EXT[1]:MAC[3]:MAC[4]:MAC[5]
|
||||
|
||||
Security fuses:
|
||||
DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0)
|
||||
nto download mode is disabled or enabled. 1: disab
|
||||
led 0: enabled
|
||||
SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0)
|
||||
e_download is disabled or enabled. 1: disabled 0:
|
||||
enabled
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0)
|
||||
led or enabled(except in SPI boot mode). 1: disabled
|
||||
0: enabled
|
||||
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
|
||||
and disables otherwise
|
||||
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0)
|
||||
KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0b00000)
|
||||
SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00)
|
||||
clock random divide mode
|
||||
XTS_DPA_PSEUDO_LEVEL (BLOCK0) Represents the pseudo round level of xts-aes anti- = 0 R/W (0b00)
|
||||
dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled
|
||||
XTS_DPA_CLK_ENABLE (BLOCK0) Represents whether xts-aes anti-dpa attack clock i = False R/W (0b0)
|
||||
s enabled. 1. Enable. 0: Disable.
|
||||
SECURE_BOOT_SHA384_EN (BLOCK0) Represents if the chip supports Secure Boot using = False R/W (0b0)
|
||||
SHA-384
|
||||
SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0)
|
||||
led. 1: enabled 0: disabled
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0)
|
||||
is enabled or disabled. 1: enabled. 0: disabled
|
||||
FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Represents whether the corresponding key must come = 0 R/W (0b00000)
|
||||
from Key Manager. Bit0: Represents whether the EC
|
||||
DSA key must come from Key Manager.0: The key does
|
||||
not need to come from Key Manager1: The key must
|
||||
come from Key ManagerBit1: Represents whether the
|
||||
XTS-AES (flash and PSRAM) key must come from Key M
|
||||
anager.0: The key does not need to come from Key M
|
||||
anager1: The key must come from Key ManagerBit2: R
|
||||
epresents whether the HMAC key must come from Key
|
||||
Manager.0: The key does not need to come from Key
|
||||
Manager1: The key must come from Key ManagerBit3:
|
||||
Represents whether the DS key must come from Key M
|
||||
anager.0: The key does not need to come from Key M
|
||||
anager1: The key must come from Key Manager
|
||||
FORCE_DISABLE_SW_INIT_KEY (BLOCK0) Represents whether to disable the use of the initi = False R/W (0b0)
|
||||
alization key written by software and instead forc
|
||||
e use efuse\_init\_key.0: Enable1: Disable
|
||||
KM_XTS_KEY_LENGTH_256 (BLOCK0) Represents which key flash encryption uses.0: XTS- = False R/W (0b0)
|
||||
AES-256 key1: XTS-AES-128 key
|
||||
LOCK_KM_KEY (BLOCK0) Represents whether the keys in the Key Manager are = False R/W (0b0)
|
||||
locked after deployment.0: Not locked1: Locked
|
||||
DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0)
|
||||
abled. 1: disabled 0: enabled
|
||||
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0)
|
||||
disabled. 1: enabled 0: disabled
|
||||
SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000)
|
||||
ck feature
|
||||
BLOCK_KEY0 (BLOCK4)
|
||||
Purpose: USER
|
||||
Key0 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY1 (BLOCK5)
|
||||
Purpose: USER
|
||||
Key1 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY2 (BLOCK6)
|
||||
Purpose: USER
|
||||
Key2 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY3 (BLOCK7)
|
||||
Purpose: USER
|
||||
Key3 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY4 (BLOCK8)
|
||||
Purpose: USER
|
||||
Key4 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY5 (BLOCK9)
|
||||
Purpose: USER
|
||||
Key5 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Usb fuses:
|
||||
DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0)
|
||||
tag is disabled or enabled. 1: disabled 0: enabled
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0)
|
||||
isabled or enabled. 1: disabled 0: enabled
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0)
|
||||
nction is disabled or enabled. 1: Disable 0: Enabl
|
||||
e
|
||||
USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins of USB_SERIA = False R/W (0b0)
|
||||
L_JTAG PHY is exchanged. 1: exchanged 0: not excha
|
||||
nged
|
||||
USB_OTG_FS_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins of USB_OTG_F = False R/W (0b0)
|
||||
S PHY is exchanged. 1: exchanged 0: not exchanged
|
||||
USB_PHY_SEL (BLOCK0) Represents whether to exchange the USB_SERIAL_JTAG = False R/W (0b0)
|
||||
PHY with USB_OTG_FS PHY. 1: exchanged. 0: not e
|
||||
xchanged
|
||||
|
||||
Vdd fuses:
|
||||
VDD_SPI_LDO_ADJUST (BLOCK1) Represents configuration of FLASH LDO mode and = 0 R/W (0x00)
|
||||
voltage.
|
||||
|
||||
Wdt fuses:
|
||||
WDT_DELAY_SEL (BLOCK1) Represents the threshold level of the RTC watchdog = 0 R/W (0b00)
|
||||
STG0 timeout. 0: Original threshold configuration
|
||||
value of STG0 *2 1: Original threshold configurat
|
||||
ion value of STG0 *4 2: Original threshold configu
|
||||
ration value of STG0 *8 3: Original threshold conf
|
||||
iguration value of STG0 *16
|
||||
|
||||
@@ -1,3 +1,21 @@
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
idf.py -p PORT efuse-dump
|
||||
|
||||
Executing action: efuse-dump
|
||||
Running espefuse in directory <project-directory>
|
||||
Executing "espefuse dump --chip esp32h4"...
|
||||
espefuse v5.3.dev3
|
||||
Connecting....
|
||||
=== Run "dump" command ===
|
||||
BLOCK0 ( ) [0 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
MAC_SPI_8M_0 (BLOCK1 ) [1 ] dump: a0ed57cc 000030ed 00000000 00040000 00000000 00000000
|
||||
BLOCK_SYS_DATA (BLOCK2 ) [2 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_USR_DATA (BLOCK3 ) [3 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY0 (BLOCK4 ) [4 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY1 (BLOCK5 ) [5 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY2 (BLOCK6 ) [6 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY3 (BLOCK7 ) [7 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY4 (BLOCK8 ) [8 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY5 (BLOCK9 ) [9 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA2 (BLOCK10 ) [10] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
:width: 2 5
|
||||
:align: center
|
||||
|
||||
* - ECO
|
||||
- Revision (Major.Minor)
|
||||
@@ -1,3 +0,0 @@
|
||||
.. note::
|
||||
|
||||
To be updated.
|
||||
@@ -1,4 +1,240 @@
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
$ ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info
|
||||
|
||||
Parsing efuse CSV input file esp32h21/esp_efuse_table.csv ...
|
||||
Verifying efuse table...
|
||||
Max number of bits in BLK 256
|
||||
Sorted efuse table:
|
||||
# field_name efuse_block bit_start bit_count
|
||||
1 WR_DIS EFUSE_BLK0 0 32
|
||||
2 WR_DIS.RD_DIS EFUSE_BLK0 0 1
|
||||
3 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1
|
||||
4 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1
|
||||
5 WR_DIS.POWERGLITCH_EN EFUSE_BLK0 2 1
|
||||
6 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1
|
||||
7 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 2 1
|
||||
8 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1
|
||||
9 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1
|
||||
10 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1
|
||||
11 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1
|
||||
12 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1
|
||||
13 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1
|
||||
14 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1
|
||||
15 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1
|
||||
16 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1
|
||||
17 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1
|
||||
18 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1
|
||||
19 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1
|
||||
20 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1
|
||||
21 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1
|
||||
22 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1
|
||||
23 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1
|
||||
24 WR_DIS.CRYPT_DPA_ENABLE EFUSE_BLK0 14 1
|
||||
25 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1
|
||||
26 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1
|
||||
27 WR_DIS.ECDSA_CURVE_MODE EFUSE_BLK0 17 1
|
||||
28 WR_DIS.ECC_FORCE_CONST_TIME EFUSE_BLK0 17 1
|
||||
29 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1
|
||||
30 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
31 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1
|
||||
32 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1
|
||||
33 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
34 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1
|
||||
35 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1
|
||||
36 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1
|
||||
37 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1
|
||||
38 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 18 1
|
||||
39 WR_DIS.HYS_EN_PAD0 EFUSE_BLK0 19 1
|
||||
40 WR_DIS.HYS_EN_PAD1 EFUSE_BLK0 19 1
|
||||
41 WR_DIS.BLK1 EFUSE_BLK0 20 1
|
||||
42 WR_DIS.MAC EFUSE_BLK0 20 1
|
||||
43 WR_DIS.MAC_EXT EFUSE_BLK0 20 1
|
||||
44 WR_DIS.RXIQ_VERSION EFUSE_BLK0 20 1
|
||||
45 WR_DIS.RXIQ_0 EFUSE_BLK0 20 1
|
||||
46 WR_DIS.RXIQ_1 EFUSE_BLK0 20 1
|
||||
47 WR_DIS.ACTIVE_HP_DBIAS EFUSE_BLK0 20 1
|
||||
48 WR_DIS.ACTIVE_LP_DBIAS EFUSE_BLK0 20 1
|
||||
49 WR_DIS.DSLP_DBIAS EFUSE_BLK0 20 1
|
||||
50 WR_DIS.DBIAS_VOL_GAP EFUSE_BLK0 20 1
|
||||
51 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1
|
||||
52 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
53 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
54 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1
|
||||
55 WR_DIS.FLASH_TEMP EFUSE_BLK0 20 1
|
||||
56 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1
|
||||
57 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1
|
||||
58 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1
|
||||
59 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1
|
||||
60 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 21 1
|
||||
61 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 21 1
|
||||
62 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 21 1
|
||||
63 WR_DIS.TEMP_CALIB EFUSE_BLK0 21 1
|
||||
64 WR_DIS.ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK0 21 1
|
||||
65 WR_DIS.ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK0 21 1
|
||||
66 WR_DIS.ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK0 21 1
|
||||
67 WR_DIS.ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK0 21 1
|
||||
68 WR_DIS.ADC1_HI_DOUT_ATTEN0 EFUSE_BLK0 21 1
|
||||
69 WR_DIS.ADC1_HI_DOUT_ATTEN1 EFUSE_BLK0 21 1
|
||||
70 WR_DIS.ADC1_HI_DOUT_ATTEN2 EFUSE_BLK0 21 1
|
||||
71 WR_DIS.ADC1_HI_DOUT_ATTEN3 EFUSE_BLK0 21 1
|
||||
72 WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
73 WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
74 WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
75 WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
76 WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
77 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1
|
||||
78 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1
|
||||
79 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1
|
||||
80 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1
|
||||
81 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1
|
||||
82 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1
|
||||
83 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1
|
||||
84 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1
|
||||
85 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1
|
||||
86 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1
|
||||
87 WR_DIS.VDD_SPI_AS_GPIO EFUSE_BLK0 30 1
|
||||
88 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1
|
||||
89 RD_DIS EFUSE_BLK0 32 7
|
||||
90 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1
|
||||
91 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1
|
||||
92 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1
|
||||
93 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1
|
||||
94 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1
|
||||
95 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1
|
||||
96 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1
|
||||
97 PVT_GLITCH_EN EFUSE_BLK0 39 1
|
||||
98 DIS_ICACHE EFUSE_BLK0 40 1
|
||||
99 DIS_USB_JTAG EFUSE_BLK0 41 1
|
||||
100 POWERGLITCH_EN EFUSE_BLK0 42 1
|
||||
101 DIS_USJ EFUSE_BLK0 43 1
|
||||
102 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1
|
||||
103 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1
|
||||
104 DIS_TWAI EFUSE_BLK0 46 1
|
||||
105 JTAG_SEL_ENABLE EFUSE_BLK0 47 1
|
||||
106 SOFT_DIS_JTAG EFUSE_BLK0 48 3
|
||||
107 DIS_PAD_JTAG EFUSE_BLK0 51 1
|
||||
108 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1
|
||||
109 USB_DREFH EFUSE_BLK0 53 2
|
||||
110 USB_DREFL EFUSE_BLK0 55 2
|
||||
111 USB_EXCHG_PINS EFUSE_BLK0 57 1
|
||||
112 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1
|
||||
113 ECDSA_CURVE_MODE EFUSE_BLK0 59 2
|
||||
114 ECC_FORCE_CONST_TIME EFUSE_BLK0 61 1
|
||||
115 XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 62 2
|
||||
116 IO_LDO_ADJUST EFUSE_BLK0 64 8
|
||||
117 VDD_SPI_LDO_ADJUST EFUSE_BLK0 72 8
|
||||
118 WDT_DELAY_SEL EFUSE_BLK0 80 2
|
||||
119 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3
|
||||
120 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1
|
||||
121 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1
|
||||
122 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1
|
||||
123 KEY_PURPOSE_0 EFUSE_BLK0 88 4
|
||||
124 KEY_PURPOSE_1 EFUSE_BLK0 92 4
|
||||
125 KEY_PURPOSE_2 EFUSE_BLK0 96 4
|
||||
126 KEY_PURPOSE_3 EFUSE_BLK0 100 4
|
||||
127 KEY_PURPOSE_4 EFUSE_BLK0 104 4
|
||||
128 KEY_PURPOSE_5 EFUSE_BLK0 108 4
|
||||
129 SEC_DPA_LEVEL EFUSE_BLK0 112 2
|
||||
130 IO_LDO_1P8 EFUSE_BLK0 114 1
|
||||
131 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1
|
||||
132 SECURE_BOOT_EN EFUSE_BLK0 116 1
|
||||
133 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1
|
||||
134 POWERGLITCH_EN1 EFUSE_BLK0 118 5
|
||||
135 FLASH_TPUW EFUSE_BLK0 124 4
|
||||
136 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1
|
||||
137 DIS_DIRECT_BOOT EFUSE_BLK0 129 1
|
||||
138 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1
|
||||
139 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1
|
||||
140 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1
|
||||
141 UART_PRINT_CONTROL EFUSE_BLK0 134 2
|
||||
142 FORCE_SEND_RESUME EFUSE_BLK0 136 1
|
||||
143 SECURE_VERSION EFUSE_BLK0 137 16
|
||||
144 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 153 1
|
||||
145 HYS_EN_PAD0 EFUSE_BLK0 154 6
|
||||
146 HYS_EN_PAD1 EFUSE_BLK0 160 22
|
||||
147 MAC EFUSE_BLK1 0 8
|
||||
148 MAC EFUSE_BLK1 8 8
|
||||
149 MAC EFUSE_BLK1 16 8
|
||||
150 MAC EFUSE_BLK1 24 8
|
||||
151 MAC EFUSE_BLK1 32 8
|
||||
152 MAC EFUSE_BLK1 40 8
|
||||
153 MAC_EXT EFUSE_BLK1 48 8
|
||||
154 MAC_EXT EFUSE_BLK1 56 8
|
||||
155 RXIQ_VERSION EFUSE_BLK1 64 3
|
||||
156 RXIQ_0 EFUSE_BLK1 67 7
|
||||
157 RXIQ_1 EFUSE_BLK1 74 7
|
||||
158 ACTIVE_HP_DBIAS EFUSE_BLK1 81 5
|
||||
159 ACTIVE_LP_DBIAS EFUSE_BLK1 86 5
|
||||
160 DSLP_DBIAS EFUSE_BLK1 91 4
|
||||
161 DBIAS_VOL_GAP EFUSE_BLK1 95 5
|
||||
162 WAFER_VERSION_MINOR EFUSE_BLK1 114 3
|
||||
163 WAFER_VERSION_MAJOR EFUSE_BLK1 117 2
|
||||
164 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 119 1
|
||||
165 FLASH_CAP EFUSE_BLK1 120 3
|
||||
166 FLASH_TEMP EFUSE_BLK1 123 2
|
||||
167 FLASH_VENDOR EFUSE_BLK1 125 3
|
||||
168 PKG_VERSION EFUSE_BLK1 128 3
|
||||
169 SYS_DATA_PART2 EFUSE_BLK10 0 256
|
||||
170 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128
|
||||
171 BLK_VERSION_MINOR EFUSE_BLK2 130 3
|
||||
172 BLK_VERSION_MAJOR EFUSE_BLK2 133 2
|
||||
173 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK2 135 1
|
||||
174 TEMP_CALIB EFUSE_BLK2 136 9
|
||||
175 ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK2 145 10
|
||||
176 ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK2 155 10
|
||||
177 ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK2 165 10
|
||||
178 ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK2 175 10
|
||||
179 ADC1_HI_DOUT_ATTEN0 EFUSE_BLK2 185 10
|
||||
180 ADC1_HI_DOUT_ATTEN1 EFUSE_BLK2 195 10
|
||||
181 ADC1_HI_DOUT_ATTEN2 EFUSE_BLK2 205 10
|
||||
182 ADC1_HI_DOUT_ATTEN3 EFUSE_BLK2 215 10
|
||||
183 ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK2 225 4
|
||||
184 ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK2 229 4
|
||||
185 ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK2 233 4
|
||||
186 ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK2 237 4
|
||||
187 ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK2 241 4
|
||||
188 USER_DATA EFUSE_BLK3 0 256
|
||||
189 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48
|
||||
190 KEY0 EFUSE_BLK4 0 256
|
||||
191 KEY1 EFUSE_BLK5 0 256
|
||||
192 KEY2 EFUSE_BLK6 0 256
|
||||
193 KEY3 EFUSE_BLK7 0 256
|
||||
194 KEY4 EFUSE_BLK8 0 256
|
||||
195 KEY5 EFUSE_BLK9 0 256
|
||||
|
||||
Used bits in efuse table:
|
||||
EFUSE_BLK0
|
||||
[0 31] [0 0] [2 2] ... [21 21] [21 22] [22 30] [30 38] [32 122] [124 130] [132 181]
|
||||
|
||||
EFUSE_BLK1
|
||||
[0 99] [114 130]
|
||||
|
||||
EFUSE_BLK10
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK2
|
||||
[0 127] [130 244]
|
||||
|
||||
EFUSE_BLK3
|
||||
[0 255] [200 247]
|
||||
|
||||
EFUSE_BLK4
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK5
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK6
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK7
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK8
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK9
|
||||
[0 255]
|
||||
|
||||
Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
|
||||
|
||||
@@ -1,4 +1,282 @@
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
$ ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info
|
||||
|
||||
Parsing efuse CSV input file esp32h4/esp_efuse_table.csv ...
|
||||
Verifying efuse table...
|
||||
Max number of bits in BLK 256
|
||||
Sorted efuse table:
|
||||
# field_name efuse_block bit_start bit_count
|
||||
1 WR_DIS EFUSE_BLK0 0 32
|
||||
2 WR_DIS.RD_DIS EFUSE_BLK0 0 1
|
||||
3 WR_DIS.KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 1 1
|
||||
4 WR_DIS.KM_RND_SWITCH_CYCLE EFUSE_BLK0 1 1
|
||||
5 WR_DIS.KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 1 1
|
||||
6 WR_DIS.FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 1 1
|
||||
7 WR_DIS.FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 1 1
|
||||
8 WR_DIS.KM_XTS_KEY_LENGTH_256 EFUSE_BLK0 1 1
|
||||
9 WR_DIS.LOCK_KM_KEY EFUSE_BLK0 1 1
|
||||
10 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1
|
||||
11 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1
|
||||
12 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 2 1
|
||||
13 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1
|
||||
14 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1
|
||||
15 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1
|
||||
16 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1
|
||||
17 WR_DIS.PVT_GLITCH_EN EFUSE_BLK0 2 1
|
||||
18 WR_DIS.PVT_GLITCH_MODE EFUSE_BLK0 2 1
|
||||
19 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1
|
||||
20 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1
|
||||
21 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1
|
||||
22 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1
|
||||
23 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1
|
||||
24 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1
|
||||
25 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1
|
||||
26 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1
|
||||
27 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1
|
||||
28 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1
|
||||
29 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1
|
||||
30 WR_DIS.XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 14 1
|
||||
31 WR_DIS.XTS_DPA_CLK_ENABLE EFUSE_BLK0 14 1
|
||||
32 WR_DIS.ECC_FORCE_CONST_TIME EFUSE_BLK0 14 1
|
||||
33 WR_DIS.SECURE_BOOT_SHA384_EN EFUSE_BLK0 14 1
|
||||
34 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1
|
||||
35 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1
|
||||
36 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1
|
||||
37 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
38 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1
|
||||
39 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1
|
||||
40 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
41 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1
|
||||
42 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1
|
||||
43 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1
|
||||
44 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1
|
||||
45 WR_DIS.HUK_GEN_STATE EFUSE_BLK0 19 1
|
||||
46 WR_DIS.BLK1 EFUSE_BLK0 20 1
|
||||
47 WR_DIS.MAC EFUSE_BLK0 20 1
|
||||
48 WR_DIS.MAC_EXT EFUSE_BLK0 20 1
|
||||
49 WR_DIS.PVT_LIMIT EFUSE_BLK0 20 1
|
||||
50 WR_DIS.PVT_CELL_SELECT EFUSE_BLK0 20 1
|
||||
51 WR_DIS.PVT_PUMP_LIMIT EFUSE_BLK0 20 1
|
||||
52 WR_DIS.PUMP_DRV EFUSE_BLK0 20 1
|
||||
53 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 20 1
|
||||
54 WR_DIS.HYS_EN_PAD EFUSE_BLK0 20 1
|
||||
55 WR_DIS.PVT_GLITCH_CHARGE_RESET EFUSE_BLK0 20 1
|
||||
56 WR_DIS.VDD_SPI_LDO_ADJUST EFUSE_BLK0 20 1
|
||||
57 WR_DIS.FLASH_LDO_POWER_SEL EFUSE_BLK0 20 1
|
||||
58 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1
|
||||
59 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
60 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
61 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
62 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1
|
||||
63 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
64 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1
|
||||
65 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1
|
||||
66 WR_DIS.PSRAM_CAP EFUSE_BLK0 20 1
|
||||
67 WR_DIS.PSRAM_VENDOR EFUSE_BLK0 20 1
|
||||
68 WR_DIS.TEMP EFUSE_BLK0 20 1
|
||||
69 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1
|
||||
70 WR_DIS.PVT_DBIAS EFUSE_BLK0 20 1
|
||||
71 WR_DIS.ADJUST_1V2 EFUSE_BLK0 20 1
|
||||
72 WR_DIS.ADJUST_1V8 EFUSE_BLK0 20 1
|
||||
73 WR_DIS.ACTIVE_DCDC_1V25 EFUSE_BLK0 20 1
|
||||
74 WR_DIS.ACTIVE_DCDC_1V35 EFUSE_BLK0 20 1
|
||||
75 WR_DIS.SLP_DCDC EFUSE_BLK0 20 1
|
||||
76 WR_DIS.LSLP_HP_DRVB EFUSE_BLK0 20 1
|
||||
77 WR_DIS.DSLP_LP_DBIAS EFUSE_BLK0 20 1
|
||||
78 WR_DIS.TEMP_CALIB EFUSE_BLK0 20 1
|
||||
79 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1
|
||||
80 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1
|
||||
81 WR_DIS.OCODE EFUSE_BLK0 21 1
|
||||
82 WR_DIS.DCDC_OCODE EFUSE_BLK0 21 1
|
||||
83 WR_DIS.VDD_3V4_DOUT EFUSE_BLK0 21 1
|
||||
84 WR_DIS.ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK0 21 1
|
||||
85 WR_DIS.ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK0 21 1
|
||||
86 WR_DIS.ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK0 21 1
|
||||
87 WR_DIS.ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK0 21 1
|
||||
88 WR_DIS.ADC1_HI_DOUT_ATTEN0 EFUSE_BLK0 21 1
|
||||
89 WR_DIS.ADC1_HI_DOUT_ATTEN1 EFUSE_BLK0 21 1
|
||||
90 WR_DIS.ADC1_HI_DOUT_ATTEN2 EFUSE_BLK0 21 1
|
||||
91 WR_DIS.ADC1_HI_DOUT_ATTEN3 EFUSE_BLK0 21 1
|
||||
92 WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
93 WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
94 WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
95 WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
96 WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
97 WR_DIS.INITCODE_DIFF_1P8_3P3 EFUSE_BLK0 21 1
|
||||
98 WR_DIS.HI_DOUT_DIFF_1P8_3P3 EFUSE_BLK0 21 1
|
||||
99 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1
|
||||
100 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1
|
||||
101 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1
|
||||
102 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1
|
||||
103 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1
|
||||
104 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1
|
||||
105 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1
|
||||
106 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1
|
||||
107 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1
|
||||
108 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1
|
||||
109 WR_DIS.USB_OTG_FS_EXCHG_PINS EFUSE_BLK0 30 1
|
||||
110 WR_DIS.USB_PHY_SEL EFUSE_BLK0 30 1
|
||||
111 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1
|
||||
112 RD_DIS EFUSE_BLK0 32 7
|
||||
113 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1
|
||||
114 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1
|
||||
115 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1
|
||||
116 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1
|
||||
117 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1
|
||||
118 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1
|
||||
119 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1
|
||||
120 DIS_USB_JTAG EFUSE_BLK0 39 1
|
||||
121 DIS_FORCE_DOWNLOAD EFUSE_BLK0 41 1
|
||||
122 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 42 1
|
||||
123 DIS_TWAI EFUSE_BLK0 43 1
|
||||
124 JTAG_SEL_ENABLE EFUSE_BLK0 44 1
|
||||
125 DIS_PAD_JTAG EFUSE_BLK0 45 1
|
||||
126 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 46 1
|
||||
127 PVT_GLITCH_EN EFUSE_BLK0 50 1
|
||||
128 PVT_GLITCH_MODE EFUSE_BLK0 52 2
|
||||
129 DIS_CORE1 EFUSE_BLK0 54 1
|
||||
130 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 55 3
|
||||
131 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 58 1
|
||||
132 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 59 1
|
||||
133 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 60 1
|
||||
134 KEY_PURPOSE_0 EFUSE_BLK0 64 5
|
||||
135 KEY_PURPOSE_1 EFUSE_BLK0 69 5
|
||||
136 KEY_PURPOSE_2 EFUSE_BLK0 74 5
|
||||
137 KEY_PURPOSE_3 EFUSE_BLK0 79 5
|
||||
138 KEY_PURPOSE_4 EFUSE_BLK0 84 5
|
||||
139 KEY_PURPOSE_5 EFUSE_BLK0 89 5
|
||||
140 SEC_DPA_LEVEL EFUSE_BLK0 94 2
|
||||
141 XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 96 2
|
||||
142 XTS_DPA_CLK_ENABLE EFUSE_BLK0 98 1
|
||||
143 ECC_FORCE_CONST_TIME EFUSE_BLK0 99 1
|
||||
144 SECURE_BOOT_SHA384_EN EFUSE_BLK0 100 1
|
||||
145 SECURE_BOOT_EN EFUSE_BLK0 101 1
|
||||
146 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 102 1
|
||||
147 KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 103 5
|
||||
148 KM_RND_SWITCH_CYCLE EFUSE_BLK0 108 2
|
||||
149 KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 110 5
|
||||
150 FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 115 5
|
||||
151 FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 120 1
|
||||
152 KM_XTS_KEY_LENGTH_256 EFUSE_BLK0 121 1
|
||||
153 LOCK_KM_KEY EFUSE_BLK0 122 1
|
||||
154 FLASH_TPUW EFUSE_BLK0 123 3
|
||||
155 DIS_DOWNLOAD_MODE EFUSE_BLK0 127 1
|
||||
156 DIS_DIRECT_BOOT EFUSE_BLK0 128 1
|
||||
157 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 129 1
|
||||
158 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 130 1
|
||||
159 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 131 1
|
||||
160 UART_PRINT_CONTROL EFUSE_BLK0 132 2
|
||||
161 FORCE_SEND_RESUME EFUSE_BLK0 134 1
|
||||
162 SECURE_VERSION EFUSE_BLK0 135 16
|
||||
163 HUK_GEN_STATE EFUSE_BLK0 151 5
|
||||
164 FLASH_LDO_EFUSE_SEL EFUSE_BLK0 156 1
|
||||
165 USB_EXCHG_PINS EFUSE_BLK0 168 1
|
||||
166 USB_OTG_FS_EXCHG_PINS EFUSE_BLK0 169 1
|
||||
167 USB_PHY_SEL EFUSE_BLK0 170 1
|
||||
168 SOFT_DIS_JTAG EFUSE_BLK0 171 3
|
||||
169 IO_LDO_ADJUST EFUSE_BLK0 174 8
|
||||
170 IO_LDO_1P8 EFUSE_BLK0 182 1
|
||||
171 DCDC_CCM_EN EFUSE_BLK0 183 1
|
||||
172 MAC EFUSE_BLK1 0 8
|
||||
173 MAC EFUSE_BLK1 8 8
|
||||
174 MAC EFUSE_BLK1 16 8
|
||||
175 MAC EFUSE_BLK1 24 8
|
||||
176 MAC EFUSE_BLK1 32 8
|
||||
177 MAC EFUSE_BLK1 40 8
|
||||
178 MAC_EXT EFUSE_BLK1 48 8
|
||||
179 MAC_EXT EFUSE_BLK1 56 8
|
||||
180 PVT_LIMIT EFUSE_BLK1 64 16
|
||||
181 PVT_CELL_SELECT EFUSE_BLK1 80 7
|
||||
182 PVT_PUMP_LIMIT EFUSE_BLK1 87 8
|
||||
183 PUMP_DRV EFUSE_BLK1 96 4
|
||||
184 WDT_DELAY_SEL EFUSE_BLK1 100 2
|
||||
185 HYS_EN_PAD EFUSE_BLK1 102 1
|
||||
186 PVT_GLITCH_CHARGE_RESET EFUSE_BLK1 103 1
|
||||
187 VDD_SPI_LDO_ADJUST EFUSE_BLK1 105 8
|
||||
188 FLASH_LDO_POWER_SEL EFUSE_BLK1 113 1
|
||||
189 WAFER_VERSION_MINOR EFUSE_BLK1 114 4
|
||||
190 WAFER_VERSION_MAJOR EFUSE_BLK1 118 2
|
||||
191 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 120 1
|
||||
192 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK1 121 1
|
||||
193 BLK_VERSION_MINOR EFUSE_BLK1 122 3
|
||||
194 BLK_VERSION_MAJOR EFUSE_BLK1 125 2
|
||||
195 FLASH_CAP EFUSE_BLK1 127 3
|
||||
196 FLASH_VENDOR EFUSE_BLK1 130 3
|
||||
197 PSRAM_CAP EFUSE_BLK1 133 3
|
||||
198 PSRAM_VENDOR EFUSE_BLK1 136 2
|
||||
199 TEMP EFUSE_BLK1 138 2
|
||||
200 PKG_VERSION EFUSE_BLK1 140 3
|
||||
201 PVT_DBIAS EFUSE_BLK1 143 5
|
||||
202 ADJUST_1V2 EFUSE_BLK1 148 4
|
||||
203 ADJUST_1V8 EFUSE_BLK1 152 4
|
||||
204 ACTIVE_DCDC_1V25 EFUSE_BLK1 156 4
|
||||
205 ACTIVE_DCDC_1V35 EFUSE_BLK1 160 4
|
||||
206 SLP_DCDC EFUSE_BLK1 164 5
|
||||
207 LSLP_HP_DRVB EFUSE_BLK1 169 5
|
||||
208 DSLP_LP_DBIAS EFUSE_BLK1 174 2
|
||||
209 TEMP_CALIB EFUSE_BLK1 176 10
|
||||
210 SYS_DATA_PART2 EFUSE_BLK10 0 256
|
||||
211 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128
|
||||
212 OCODE EFUSE_BLK2 128 8
|
||||
213 DCDC_OCODE EFUSE_BLK2 136 8
|
||||
214 VDD_3V4_DOUT EFUSE_BLK2 144 10
|
||||
215 ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK2 154 9
|
||||
216 ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK2 163 9
|
||||
217 ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK2 172 9
|
||||
218 ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK2 181 9
|
||||
219 ADC1_HI_DOUT_ATTEN0 EFUSE_BLK2 190 9
|
||||
220 ADC1_HI_DOUT_ATTEN1 EFUSE_BLK2 199 9
|
||||
221 ADC1_HI_DOUT_ATTEN2 EFUSE_BLK2 208 9
|
||||
222 ADC1_HI_DOUT_ATTEN3 EFUSE_BLK2 217 9
|
||||
223 ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK2 226 3
|
||||
224 ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK2 229 3
|
||||
225 ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK2 232 3
|
||||
226 ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK2 235 3
|
||||
227 ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK2 238 3
|
||||
228 INITCODE_DIFF_1P8_3P3 EFUSE_BLK2 241 5
|
||||
229 HI_DOUT_DIFF_1P8_3P3 EFUSE_BLK2 246 5
|
||||
230 USER_DATA EFUSE_BLK3 0 256
|
||||
231 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48
|
||||
232 KEY0 EFUSE_BLK4 0 256
|
||||
233 KEY1 EFUSE_BLK5 0 256
|
||||
234 KEY2 EFUSE_BLK6 0 256
|
||||
235 KEY3 EFUSE_BLK7 0 256
|
||||
236 KEY4 EFUSE_BLK8 0 256
|
||||
237 KEY5 EFUSE_BLK9 0 256
|
||||
|
||||
Used bits in efuse table:
|
||||
EFUSE_BLK0
|
||||
[0 31] [0 1] [1 1] ... [50 50] [52 60] [64 125] [127 156] [168 183]
|
||||
|
||||
EFUSE_BLK1
|
||||
[0 94] [96 103] [105 185]
|
||||
|
||||
EFUSE_BLK10
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK2
|
||||
[0 250]
|
||||
|
||||
EFUSE_BLK3
|
||||
[0 255] [200 247]
|
||||
|
||||
EFUSE_BLK4
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK5
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK6
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK7
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK8
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK9
|
||||
[0 255]
|
||||
|
||||
Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
|
||||
|
||||
@@ -75,7 +75,7 @@ eFuse 字段通过 CSV 文件中特定格式的表格进行定义。通过这种
|
||||
|
||||
一般情况下,每个记录在定义表格中占据一行,每行包含以下值(也就是列):
|
||||
|
||||
{IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3", esp32c2 = "EFUSE_BLK3"}
|
||||
{IDF_TARGET_MAX_EFUSE_BLK:default = "EFUSE_BLK10", esp32 = "EFUSE_BLK3", esp32c2 = "EFUSE_BLK3", esp32s31 = "EFUSE_BLK9"}
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
|
||||
@@ -1,3 +1,164 @@
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
idf.py -p PORT efuse-summary
|
||||
|
||||
Executing action: efuse-summary
|
||||
(...)
|
||||
|
||||
=== Run "summary" command ===
|
||||
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
||||
----------------------------------------------------------------------------------------
|
||||
Config fuses:
|
||||
WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000)
|
||||
RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
|
||||
DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled. = False R/W (0b0)
|
||||
1: disabled. 0: enabled
|
||||
POWERGLITCH_EN (BLOCK0) Represents whether power glitch function is = False R/W (0b0)
|
||||
enabled. 1: enabled. 0: disabled
|
||||
DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or = False R/W (0b0)
|
||||
enabled. 1: disabled. 0: enabled
|
||||
RPT4_RESERVED0_2 (BLOCK0) Reserved = 0 R/W (0b00)
|
||||
RPT4_RESERVED0_1 (BLOCK0) Reserved = False R/W (0b0)
|
||||
DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
|
||||
enabled. 1: disabled. 0: enabled
|
||||
UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00)
|
||||
HYS_EN_PAD0 (BLOCK0) Set bits to enable hysteresis function of PAD0~5 = 0 R/W (0b000000)
|
||||
HYS_EN_PAD1 (BLOCK0) Set bits to enable hysteresis function of PAD6~27 = 0 R/W (0b0000000000000000000000)
|
||||
RXIQ_0 (BLOCK1) Stores RF Calibration data. RXIQ data 0 = 0 R/W (0b0000000)
|
||||
RXIQ_1 (BLOCK1) Stores RF Calibration data. RXIQ data 1 = 0 R/W (0b0000000)
|
||||
BLOCK_USR_DATA (BLOCK3) User data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved)
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Flash fuses:
|
||||
FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0)
|
||||
in unit of ms. When the value less than 15; the
|
||||
waiting time is the programmed value. Otherwise; the
|
||||
waiting time is 2 times the programmed value
|
||||
FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a = False R/W (0b0)
|
||||
resume command during SPI boot. 1: forced. 0:not
|
||||
forced
|
||||
FLASH_CAP (BLOCK1) Stores the flash cap = 0 R/W (0b000)
|
||||
FLASH_TEMP (BLOCK1) Stores the flash temp = 0 R/W (0b00)
|
||||
FLASH_VENDOR (BLOCK1) Stores the flash vendor = 0 R/W (0b000)
|
||||
|
||||
Identity fuses:
|
||||
RXIQ_VERSION (BLOCK1) Stores RF Calibration data. RXIQ version = 0 R/W (0b000)
|
||||
WAFER_VERSION_MINOR (BLOCK1) Stores the wafer version minor = 0 R/W (0b000)
|
||||
WAFER_VERSION_MAJOR (BLOCK1) Stores the wafer version major = 0 R/W (0b00)
|
||||
DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0)
|
||||
PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000)
|
||||
OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration = 0 R/W (0b000)
|
||||
data in BLOCK1
|
||||
BLK_VERSION_MAJOR (BLOCK2) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00)
|
||||
DISABLE_BLK_VERSION_MAJOR (BLOCK2) Disables check of blk version major = False R/W (0b0)
|
||||
|
||||
Jtag fuses:
|
||||
JTAG_SEL_ENABLE (BLOCK0) Set this bit to enable selection between = False R/W (0b0)
|
||||
usb_to_jtag and pad_to_jtag through strapping
|
||||
gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are
|
||||
equal to 0
|
||||
SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. = 0 R/W (0b000)
|
||||
Odd number: disabled. Even number: enabled
|
||||
DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the = False R/W (0b0)
|
||||
hard way(permanently). 1: disabled. 0: enabled
|
||||
|
||||
Mac fuses:
|
||||
MAC (BLOCK1) MAC address
|
||||
= 00:00:00:00:00:00 (OK) R/W
|
||||
MAC_EXT (BLOCK1) Stores the extended bits of MAC address = 00:00 (OK) R/W
|
||||
CUSTOM_MAC (BLOCK3) Custom MAC
|
||||
= 00:00:00:00:00:00 (OK) R/W
|
||||
MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M
|
||||
= 00:00:00:00:00:00:00:00 (OK) R/W
|
||||
AC_EXT[1]:MAC[3]:MAC[4]:MAC[5]
|
||||
|
||||
Security fuses:
|
||||
DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip = False R/W (0b0)
|
||||
into download mode is disabled or enabled. 1:
|
||||
disabled. 0: enabled
|
||||
SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during = False R/W (0b0)
|
||||
boot_mode_download is disabled or enabled. 1: disabled. 0:
|
||||
enabled
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is = False R/W (0b0)
|
||||
disabled or enabled(except in SPI boot mode). 1:
|
||||
disabled. 0: enabled
|
||||
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
|
||||
and disables otherwise
|
||||
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0)
|
||||
KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0)
|
||||
KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0)
|
||||
KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0)
|
||||
KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0)
|
||||
KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0)
|
||||
KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0)
|
||||
SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00)
|
||||
clock random divide mode
|
||||
ECDSA_FORCE_USE_HARDWARE_K (BLOCK0) Represents whether hardware random number k is = False R/W (0b0)
|
||||
forced used in ESDCA. 1: force used. 0: not force
|
||||
used
|
||||
CRYPT_DPA_ENABLE (BLOCK0) Represents whether anti-dpa attack is enabled. = False R/W (0b0)
|
||||
1:enabled. 0: disabled
|
||||
SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or = False R/W (0b0)
|
||||
disabled. 1: enabled. 0: disabled
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0)
|
||||
is enabled or disabled. 1: enabled. 0: disabled
|
||||
DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or = False R/W (0b0)
|
||||
enabled. 1: disabled. 0: enabled
|
||||
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0)
|
||||
disabled. 1: enabled. 0: disabled
|
||||
SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF = 0 R/W (0x0000)
|
||||
anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0)
|
||||
or enabled when Secure Boot is enabled. 1:
|
||||
disabled. 0: enabled
|
||||
BLOCK_KEY0 (BLOCK4)
|
||||
Purpose: USER
|
||||
Key0 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY1 (BLOCK5)
|
||||
Purpose: USER
|
||||
Key1 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY2 (BLOCK6)
|
||||
Purpose: USER
|
||||
Key2 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY3 (BLOCK7)
|
||||
Purpose: USER
|
||||
Key3 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY4 (BLOCK8)
|
||||
Purpose: USER
|
||||
Key4 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY5 (BLOCK9)
|
||||
Purpose: USER
|
||||
Key5 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Usb fuses:
|
||||
DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to = False R/W (0b0)
|
||||
jtag is disabled or enabled. 1: disabled. 0:
|
||||
enabled
|
||||
USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0)
|
||||
1: exchanged. 0: not exchanged
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Set this bit to disable USB-Serial-JTAG print = False R/W (0b0)
|
||||
during rom boot
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download = False R/W (0b0)
|
||||
function is disabled or enabled. 1: disabled. 0:
|
||||
enabled
|
||||
|
||||
Vdd fuses:
|
||||
VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as = False R/W (0b0)
|
||||
gpio. 1: functioned. 0: not functioned
|
||||
|
||||
Wdt fuses:
|
||||
WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b00)
|
||||
is selected at startup. 1: selected. 0: not
|
||||
selected
|
||||
|
||||
@@ -1,3 +1,21 @@
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
idf.py -p PORT efuse-dump
|
||||
|
||||
Executing action: efuse-dump
|
||||
Running espefuse in directory <project-directory>
|
||||
Executing "espefuse dump --chip esp32h21"...
|
||||
espefuse v5.3.dev3
|
||||
Connecting....
|
||||
=== Run "dump" command ===
|
||||
BLOCK0 ( ) [0 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
MAC_SPI_8M_0 (BLOCK1 ) [1 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA (BLOCK2 ) [2 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_USR_DATA (BLOCK3 ) [3 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY0 (BLOCK4 ) [4 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY1 (BLOCK5 ) [5 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY2 (BLOCK6 ) [6 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY3 (BLOCK7 ) [7 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY4 (BLOCK8 ) [8 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY5 (BLOCK9 ) [9 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA2 (BLOCK10 ) [10] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
|
||||
@@ -1,3 +1,248 @@
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
idf.py -p PORT efuse-summary
|
||||
|
||||
Executing action: efuse-summary
|
||||
(...)
|
||||
|
||||
=== Run "summary" command ===
|
||||
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
|
||||
----------------------------------------------------------------------------------------
|
||||
Config fuses:
|
||||
WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000)
|
||||
RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
|
||||
DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0)
|
||||
abled. 1: disabled 0: enabled
|
||||
PVT_GLITCH_EN (BLOCK0) Represents whether to enable PVT power glitch moni = False R/W (0b0)
|
||||
tor function.1:Enable. 0:Disable
|
||||
PVT_GLITCH_MODE (BLOCK0) Use to configure glitch mode = 0 R/W (0b00)
|
||||
DIS_CORE1 (BLOCK0) Represents whether the CPU-Core1 is disabled. 1: = False R/W (0b0)
|
||||
Disabled. 0: Not disable
|
||||
ECC_FORCE_CONST_TIME (BLOCK0) Represents whether to force ecc to use const-time = False R/W (0b0)
|
||||
calculation mode. 1: Enable. 0: Disable
|
||||
KM_DISABLE_DEPLOY_MODE (BLOCK0) Represents whether the new key deployment of key m = 0 R/W (0b00000)
|
||||
anager is disabled. Bit0: Represents whether the n
|
||||
ew ECDSA key deployment is disabled0: Enabled1: Di
|
||||
sabledBit1: Represents whether the new XTS-AES (fl
|
||||
ash and PSRAM) key deployment is disabled0: Enable
|
||||
d1: DisabledBit2: Represents whether the new HMAC
|
||||
key deployment is disabled0: Enabled1: DisabledBit
|
||||
3: Represents whether the new DS key deployment is
|
||||
disabled0: Enabled1: Disabled
|
||||
KM_RND_SWITCH_CYCLE (BLOCK0) Represents the cycle at which the Key Manager swit = 0 R/W (0b00)
|
||||
ches random numbers.0: Controlled by the \hyperref
|
||||
[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWIT
|
||||
CH\_CYCLE} register. For more information; please
|
||||
refer to Chapter \ref{mod:keymng} \textit{\nameref
|
||||
{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Ke
|
||||
y Manager clock cycles3: 32 Key Manager clock cycl
|
||||
es
|
||||
KM_DEPLOY_ONLY_ONCE (BLOCK0) Represents whether the corresponding key can be de = 0 R/W (0b00000)
|
||||
ployed only once.Bit0: Represents whether the ECDS
|
||||
A key can be deployed only once0: The key can be d
|
||||
eployed multiple times1: The key can be deployed o
|
||||
nly onceBit1: Represents whether the XTS-AES (flas
|
||||
h and PSRAM) key can be deployed only once0: The k
|
||||
ey can be deployed multiple times1: The key can be
|
||||
deployed only onceBit2: Represents whether the HM
|
||||
AC key can be deployed only once0: The key can be
|
||||
deployed multiple times1: The key can be deployed
|
||||
only onceBit3: Represents whether the DS key can b
|
||||
e deployed only once0: The key can be deployed
|
||||
multiple times1: The key can be deployed only once
|
||||
DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
|
||||
enabled. 1: disabled 0: enabled
|
||||
UART_PRINT_CONTROL (BLOCK0) Represents the type of UART printing. 00: force en = 0 R/W (0b00)
|
||||
able printing 01: enable printing when GPIO8 is re
|
||||
set at low level 10: enable printing when GPIO8 is
|
||||
reset at high level 11: force disable printing
|
||||
HUK_GEN_STATE (BLOCK0) Represents whether the HUK generate mode is valid. = 0 R/W (0b00000)
|
||||
Odd count of bits with a value of 1: InvalidEven c
|
||||
ount of bits with a value of 1: Valid
|
||||
DCDC_CCM_EN (BLOCK0) Represents whether change DCDC to CCM mode = False R/W (0b0)
|
||||
PVT_LIMIT (BLOCK1) Power glitch monitor threthold = 0 R/W (0x0000)
|
||||
PVT_CELL_SELECT (BLOCK1) Power glitch monitor PVT cell select = 0 R/W (0b0000000)
|
||||
PVT_PUMP_LIMIT (BLOCK1) Use to configure voltage monitor limit for charge = 0 R/W (0x00)
|
||||
pump
|
||||
PUMP_DRV (BLOCK1) Use to configure charge pump voltage gain = 0 R/W (0x0)
|
||||
HYS_EN_PAD (BLOCK1) Represents whether the hysteresis function of = False R/W (0b0)
|
||||
corresponding PAD is enabled. 1: enabled 0:disabled
|
||||
PVT_GLITCH_CHARGE_RESET (BLOCK1) Represents whether to trigger reset or charge pump = False R/W (0b0)
|
||||
when PVT power glitch happened.1:Trigger charge p
|
||||
ump. 0:Trigger reset
|
||||
PSRAM_CAP (BLOCK1) Psram capacity = 0 R/W (0b000)
|
||||
PSRAM_VENDOR (BLOCK1) Psram vendor = 0 R/W (0b00)
|
||||
TEMP (BLOCK1) Temp (die embedded inside) = 0 R/W (0b00)
|
||||
ADJUST_1V2 (BLOCK1) SPI LDO adjust of 1.2v = 0 R/W (0x0)
|
||||
ADJUST_1V8 (BLOCK1) SPI LDO adjust of 1.8v = 0 R/W (0x0)
|
||||
ACTIVE_DCDC_1V25 (BLOCK1) DCDC-DCDC DBIAS of 1.25v = 0 R/W (0x0)
|
||||
ACTIVE_DCDC_1V35 (BLOCK1) DCDC-DCDC DBIAS of 1.35v = 0 R/W (0x0)
|
||||
SLP_DCDC (BLOCK1) DCDC DBIAS in sleep = 0 R/W (0b00000)
|
||||
VDD_3V4_DOUT (BLOCK2) ADC dout of vdd 3.4v = 0 R/W (0b0000000000)
|
||||
INITCODE_DIFF_1P8_3P3 (BLOCK2) Initcode diff between IO LDO 1.8v and 3.3v = 0 R/W (0b00000)
|
||||
HI_DOUT_DIFF_1P8_3P3 (BLOCK2) HI dout diff between IO LDO 1.8v and 3.3v = 0 R/W (0b00000)
|
||||
BLOCK_USR_DATA (BLOCK3) User data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved)
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Flash fuses:
|
||||
FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0b000)
|
||||
in unit of ms. When the value less than 15; the wa
|
||||
iting time is the programmed value. Otherwise; the
|
||||
waiting time is 2 times the programmed value
|
||||
FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0)
|
||||
sume command during SPI boot. 1: forced 0:not forc
|
||||
ed
|
||||
FLASH_LDO_EFUSE_SEL (BLOCK0) Represents whether to select efuse control flash l = False R/W (0b0)
|
||||
do default voltage. 1 : efuse 0 : strapping
|
||||
FLASH_LDO_POWER_SEL (BLOCK1) Represents which flash ldo be select: 1: FLASH LDO = False R/W (0b0)
|
||||
1P2 0 : FLASH LDO 1P8
|
||||
FLASH_CAP (BLOCK1) Flash capacity = 0 R/W (0b000)
|
||||
FLASH_VENDOR (BLOCK1) Flash vendor = 0 R/W (0b000)
|
||||
|
||||
Identity fuses:
|
||||
WAFER_VERSION_MINOR (BLOCK1) Minor chip version = 1 R/W (0x1)
|
||||
WAFER_VERSION_MAJOR (BLOCK1) Major chip version = 0 R/W (0b00)
|
||||
DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0)
|
||||
DISABLE_BLK_VERSION_MAJOR (BLOCK1) Disables check of blk version major = False R/W (0b0)
|
||||
BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000)
|
||||
BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00)
|
||||
PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000)
|
||||
OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Jtag fuses:
|
||||
JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0)
|
||||
ag and pad_to_jtag through strapping gpio15 when b
|
||||
oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are
|
||||
equal to 0 is enabled or disabled. 1: enabled 0: d
|
||||
isabled
|
||||
DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0)
|
||||
y(permanently). 1: disabled 0: enabled
|
||||
SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000)
|
||||
dd number: disabled Even number: enabled
|
||||
|
||||
Mac fuses:
|
||||
MAC (BLOCK1) MAC address
|
||||
= 30:ed:a0:ed:57:cc (OK) R/W
|
||||
MAC_EXT (BLOCK1) Represents the extended bits of MAC address = 00:00 (OK) R/W
|
||||
CUSTOM_MAC (BLOCK3) Custom MAC
|
||||
= 00:00:00:00:00:00 (OK) R/W
|
||||
MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M
|
||||
= 30:ed:a0:00:00:ed:57:cc (OK) R/W
|
||||
AC_EXT[1]:MAC[3]:MAC[4]:MAC[5]
|
||||
|
||||
Security fuses:
|
||||
DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0)
|
||||
nto download mode is disabled or enabled. 1: disab
|
||||
led 0: enabled
|
||||
SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0)
|
||||
e_download is disabled or enabled. 1: disabled 0:
|
||||
enabled
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0)
|
||||
led or enabled(except in SPI boot mode). 1: disabled
|
||||
0: enabled
|
||||
SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000)
|
||||
and disables otherwise
|
||||
SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0)
|
||||
SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0)
|
||||
KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0b00000)
|
||||
KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0b00000)
|
||||
SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00)
|
||||
clock random divide mode
|
||||
XTS_DPA_PSEUDO_LEVEL (BLOCK0) Represents the pseudo round level of xts-aes anti- = 0 R/W (0b00)
|
||||
dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled
|
||||
XTS_DPA_CLK_ENABLE (BLOCK0) Represents whether xts-aes anti-dpa attack clock i = False R/W (0b0)
|
||||
s enabled. 1. Enable. 0: Disable.
|
||||
SECURE_BOOT_SHA384_EN (BLOCK0) Represents if the chip supports Secure Boot using = False R/W (0b0)
|
||||
SHA-384
|
||||
SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0)
|
||||
led. 1: enabled 0: disabled
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0)
|
||||
is enabled or disabled. 1: enabled. 0: disabled
|
||||
FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Represents whether the corresponding key must come = 0 R/W (0b00000)
|
||||
from Key Manager. Bit0: Represents whether the EC
|
||||
DSA key must come from Key Manager.0: The key does
|
||||
not need to come from Key Manager1: The key must
|
||||
come from Key ManagerBit1: Represents whether the
|
||||
XTS-AES (flash and PSRAM) key must come from Key M
|
||||
anager.0: The key does not need to come from Key M
|
||||
anager1: The key must come from Key ManagerBit2: R
|
||||
epresents whether the HMAC key must come from Key
|
||||
Manager.0: The key does not need to come from Key
|
||||
Manager1: The key must come from Key ManagerBit3:
|
||||
Represents whether the DS key must come from Key M
|
||||
anager.0: The key does not need to come from Key M
|
||||
anager1: The key must come from Key Manager
|
||||
FORCE_DISABLE_SW_INIT_KEY (BLOCK0) Represents whether to disable the use of the initi = False R/W (0b0)
|
||||
alization key written by software and instead forc
|
||||
e use efuse\_init\_key.0: Enable1: Disable
|
||||
KM_XTS_KEY_LENGTH_256 (BLOCK0) Represents which key flash encryption uses.0: XTS- = False R/W (0b0)
|
||||
AES-256 key1: XTS-AES-128 key
|
||||
LOCK_KM_KEY (BLOCK0) Represents whether the keys in the Key Manager are = False R/W (0b0)
|
||||
locked after deployment.0: Not locked1: Locked
|
||||
DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0)
|
||||
abled. 1: disabled 0: enabled
|
||||
ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0)
|
||||
disabled. 1: enabled 0: disabled
|
||||
SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000)
|
||||
ck feature
|
||||
BLOCK_KEY0 (BLOCK4)
|
||||
Purpose: USER
|
||||
Key0 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY1 (BLOCK5)
|
||||
Purpose: USER
|
||||
Key1 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY2 (BLOCK6)
|
||||
Purpose: USER
|
||||
Key2 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY3 (BLOCK7)
|
||||
Purpose: USER
|
||||
Key3 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY4 (BLOCK8)
|
||||
Purpose: USER
|
||||
Key4 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
BLOCK_KEY5 (BLOCK9)
|
||||
Purpose: USER
|
||||
Key5 or user data
|
||||
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
|
||||
|
||||
Usb fuses:
|
||||
DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0)
|
||||
tag is disabled or enabled. 1: disabled 0: enabled
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0)
|
||||
isabled or enabled. 1: disabled 0: enabled
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0)
|
||||
nction is disabled or enabled. 1: Disable 0: Enabl
|
||||
e
|
||||
USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins of USB_SERIA = False R/W (0b0)
|
||||
L_JTAG PHY is exchanged. 1: exchanged 0: not excha
|
||||
nged
|
||||
USB_OTG_FS_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins of USB_OTG_F = False R/W (0b0)
|
||||
S PHY is exchanged. 1: exchanged 0: not exchanged
|
||||
USB_PHY_SEL (BLOCK0) Represents whether to exchange the USB_SERIAL_JTAG = False R/W (0b0)
|
||||
PHY with USB_OTG_FS PHY. 1: exchanged. 0: not e
|
||||
xchanged
|
||||
|
||||
Vdd fuses:
|
||||
VDD_SPI_LDO_ADJUST (BLOCK1) Represents configuration of FLASH LDO mode and = 0 R/W (0x00)
|
||||
voltage.
|
||||
|
||||
Wdt fuses:
|
||||
WDT_DELAY_SEL (BLOCK1) Represents the threshold level of the RTC watchdog = 0 R/W (0b00)
|
||||
STG0 timeout. 0: Original threshold configuration
|
||||
value of STG0 *2 1: Original threshold configurat
|
||||
ion value of STG0 *4 2: Original threshold configu
|
||||
ration value of STG0 *8 3: Original threshold conf
|
||||
iguration value of STG0 *16
|
||||
|
||||
@@ -1,3 +1,21 @@
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
idf.py -p PORT efuse-dump
|
||||
|
||||
Executing action: efuse-dump
|
||||
Running espefuse in directory <project-directory>
|
||||
Executing "espefuse dump --chip esp32h4"...
|
||||
espefuse v5.3.dev3
|
||||
Connecting....
|
||||
=== Run "dump" command ===
|
||||
BLOCK0 ( ) [0 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
MAC_SPI_8M_0 (BLOCK1 ) [1 ] dump: a0ed57cc 000030ed 00000000 00040000 00000000 00000000
|
||||
BLOCK_SYS_DATA (BLOCK2 ) [2 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_USR_DATA (BLOCK3 ) [3 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY0 (BLOCK4 ) [4 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY1 (BLOCK5 ) [5 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY2 (BLOCK6 ) [6 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY3 (BLOCK7 ) [7 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY4 (BLOCK8 ) [8 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_KEY5 (BLOCK9 ) [9 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
BLOCK_SYS_DATA2 (BLOCK10 ) [10] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
|
||||
.. list-table::
|
||||
:header-rows: 1
|
||||
:width: 2 5
|
||||
:align: center
|
||||
|
||||
* - ECO
|
||||
- Revision (Major.Minor)
|
||||
@@ -1,3 +0,0 @@
|
||||
.. note::
|
||||
|
||||
To be updated.
|
||||
@@ -1,4 +1,240 @@
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
$ ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info
|
||||
|
||||
Parsing efuse CSV input file esp32h21/esp_efuse_table.csv ...
|
||||
Verifying efuse table...
|
||||
Max number of bits in BLK 256
|
||||
Sorted efuse table:
|
||||
# field_name efuse_block bit_start bit_count
|
||||
1 WR_DIS EFUSE_BLK0 0 32
|
||||
2 WR_DIS.RD_DIS EFUSE_BLK0 0 1
|
||||
3 WR_DIS.DIS_ICACHE EFUSE_BLK0 2 1
|
||||
4 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1
|
||||
5 WR_DIS.POWERGLITCH_EN EFUSE_BLK0 2 1
|
||||
6 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1
|
||||
7 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 2 1
|
||||
8 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1
|
||||
9 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1
|
||||
10 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1
|
||||
11 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1
|
||||
12 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 3 1
|
||||
13 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1
|
||||
14 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1
|
||||
15 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1
|
||||
16 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1
|
||||
17 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1
|
||||
18 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1
|
||||
19 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1
|
||||
20 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1
|
||||
21 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1
|
||||
22 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1
|
||||
23 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1
|
||||
24 WR_DIS.CRYPT_DPA_ENABLE EFUSE_BLK0 14 1
|
||||
25 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1
|
||||
26 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1
|
||||
27 WR_DIS.ECDSA_CURVE_MODE EFUSE_BLK0 17 1
|
||||
28 WR_DIS.ECC_FORCE_CONST_TIME EFUSE_BLK0 17 1
|
||||
29 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1
|
||||
30 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
31 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1
|
||||
32 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1
|
||||
33 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
34 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1
|
||||
35 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1
|
||||
36 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1
|
||||
37 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1
|
||||
38 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 18 1
|
||||
39 WR_DIS.HYS_EN_PAD0 EFUSE_BLK0 19 1
|
||||
40 WR_DIS.HYS_EN_PAD1 EFUSE_BLK0 19 1
|
||||
41 WR_DIS.BLK1 EFUSE_BLK0 20 1
|
||||
42 WR_DIS.MAC EFUSE_BLK0 20 1
|
||||
43 WR_DIS.MAC_EXT EFUSE_BLK0 20 1
|
||||
44 WR_DIS.RXIQ_VERSION EFUSE_BLK0 20 1
|
||||
45 WR_DIS.RXIQ_0 EFUSE_BLK0 20 1
|
||||
46 WR_DIS.RXIQ_1 EFUSE_BLK0 20 1
|
||||
47 WR_DIS.ACTIVE_HP_DBIAS EFUSE_BLK0 20 1
|
||||
48 WR_DIS.ACTIVE_LP_DBIAS EFUSE_BLK0 20 1
|
||||
49 WR_DIS.DSLP_DBIAS EFUSE_BLK0 20 1
|
||||
50 WR_DIS.DBIAS_VOL_GAP EFUSE_BLK0 20 1
|
||||
51 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1
|
||||
52 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
53 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
54 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1
|
||||
55 WR_DIS.FLASH_TEMP EFUSE_BLK0 20 1
|
||||
56 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1
|
||||
57 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1
|
||||
58 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1
|
||||
59 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1
|
||||
60 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 21 1
|
||||
61 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 21 1
|
||||
62 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 21 1
|
||||
63 WR_DIS.TEMP_CALIB EFUSE_BLK0 21 1
|
||||
64 WR_DIS.ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK0 21 1
|
||||
65 WR_DIS.ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK0 21 1
|
||||
66 WR_DIS.ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK0 21 1
|
||||
67 WR_DIS.ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK0 21 1
|
||||
68 WR_DIS.ADC1_HI_DOUT_ATTEN0 EFUSE_BLK0 21 1
|
||||
69 WR_DIS.ADC1_HI_DOUT_ATTEN1 EFUSE_BLK0 21 1
|
||||
70 WR_DIS.ADC1_HI_DOUT_ATTEN2 EFUSE_BLK0 21 1
|
||||
71 WR_DIS.ADC1_HI_DOUT_ATTEN3 EFUSE_BLK0 21 1
|
||||
72 WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
73 WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
74 WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
75 WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
76 WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
77 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1
|
||||
78 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1
|
||||
79 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1
|
||||
80 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1
|
||||
81 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1
|
||||
82 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1
|
||||
83 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1
|
||||
84 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1
|
||||
85 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1
|
||||
86 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1
|
||||
87 WR_DIS.VDD_SPI_AS_GPIO EFUSE_BLK0 30 1
|
||||
88 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1
|
||||
89 RD_DIS EFUSE_BLK0 32 7
|
||||
90 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1
|
||||
91 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1
|
||||
92 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1
|
||||
93 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1
|
||||
94 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1
|
||||
95 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1
|
||||
96 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1
|
||||
97 PVT_GLITCH_EN EFUSE_BLK0 39 1
|
||||
98 DIS_ICACHE EFUSE_BLK0 40 1
|
||||
99 DIS_USB_JTAG EFUSE_BLK0 41 1
|
||||
100 POWERGLITCH_EN EFUSE_BLK0 42 1
|
||||
101 DIS_USJ EFUSE_BLK0 43 1
|
||||
102 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1
|
||||
103 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1
|
||||
104 DIS_TWAI EFUSE_BLK0 46 1
|
||||
105 JTAG_SEL_ENABLE EFUSE_BLK0 47 1
|
||||
106 SOFT_DIS_JTAG EFUSE_BLK0 48 3
|
||||
107 DIS_PAD_JTAG EFUSE_BLK0 51 1
|
||||
108 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1
|
||||
109 USB_DREFH EFUSE_BLK0 53 2
|
||||
110 USB_DREFL EFUSE_BLK0 55 2
|
||||
111 USB_EXCHG_PINS EFUSE_BLK0 57 1
|
||||
112 VDD_SPI_AS_GPIO EFUSE_BLK0 58 1
|
||||
113 ECDSA_CURVE_MODE EFUSE_BLK0 59 2
|
||||
114 ECC_FORCE_CONST_TIME EFUSE_BLK0 61 1
|
||||
115 XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 62 2
|
||||
116 IO_LDO_ADJUST EFUSE_BLK0 64 8
|
||||
117 VDD_SPI_LDO_ADJUST EFUSE_BLK0 72 8
|
||||
118 WDT_DELAY_SEL EFUSE_BLK0 80 2
|
||||
119 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 82 3
|
||||
120 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 85 1
|
||||
121 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 86 1
|
||||
122 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 87 1
|
||||
123 KEY_PURPOSE_0 EFUSE_BLK0 88 4
|
||||
124 KEY_PURPOSE_1 EFUSE_BLK0 92 4
|
||||
125 KEY_PURPOSE_2 EFUSE_BLK0 96 4
|
||||
126 KEY_PURPOSE_3 EFUSE_BLK0 100 4
|
||||
127 KEY_PURPOSE_4 EFUSE_BLK0 104 4
|
||||
128 KEY_PURPOSE_5 EFUSE_BLK0 108 4
|
||||
129 SEC_DPA_LEVEL EFUSE_BLK0 112 2
|
||||
130 IO_LDO_1P8 EFUSE_BLK0 114 1
|
||||
131 CRYPT_DPA_ENABLE EFUSE_BLK0 115 1
|
||||
132 SECURE_BOOT_EN EFUSE_BLK0 116 1
|
||||
133 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 117 1
|
||||
134 POWERGLITCH_EN1 EFUSE_BLK0 118 5
|
||||
135 FLASH_TPUW EFUSE_BLK0 124 4
|
||||
136 DIS_DOWNLOAD_MODE EFUSE_BLK0 128 1
|
||||
137 DIS_DIRECT_BOOT EFUSE_BLK0 129 1
|
||||
138 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 130 1
|
||||
139 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 132 1
|
||||
140 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 133 1
|
||||
141 UART_PRINT_CONTROL EFUSE_BLK0 134 2
|
||||
142 FORCE_SEND_RESUME EFUSE_BLK0 136 1
|
||||
143 SECURE_VERSION EFUSE_BLK0 137 16
|
||||
144 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 153 1
|
||||
145 HYS_EN_PAD0 EFUSE_BLK0 154 6
|
||||
146 HYS_EN_PAD1 EFUSE_BLK0 160 22
|
||||
147 MAC EFUSE_BLK1 0 8
|
||||
148 MAC EFUSE_BLK1 8 8
|
||||
149 MAC EFUSE_BLK1 16 8
|
||||
150 MAC EFUSE_BLK1 24 8
|
||||
151 MAC EFUSE_BLK1 32 8
|
||||
152 MAC EFUSE_BLK1 40 8
|
||||
153 MAC_EXT EFUSE_BLK1 48 8
|
||||
154 MAC_EXT EFUSE_BLK1 56 8
|
||||
155 RXIQ_VERSION EFUSE_BLK1 64 3
|
||||
156 RXIQ_0 EFUSE_BLK1 67 7
|
||||
157 RXIQ_1 EFUSE_BLK1 74 7
|
||||
158 ACTIVE_HP_DBIAS EFUSE_BLK1 81 5
|
||||
159 ACTIVE_LP_DBIAS EFUSE_BLK1 86 5
|
||||
160 DSLP_DBIAS EFUSE_BLK1 91 4
|
||||
161 DBIAS_VOL_GAP EFUSE_BLK1 95 5
|
||||
162 WAFER_VERSION_MINOR EFUSE_BLK1 114 3
|
||||
163 WAFER_VERSION_MAJOR EFUSE_BLK1 117 2
|
||||
164 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 119 1
|
||||
165 FLASH_CAP EFUSE_BLK1 120 3
|
||||
166 FLASH_TEMP EFUSE_BLK1 123 2
|
||||
167 FLASH_VENDOR EFUSE_BLK1 125 3
|
||||
168 PKG_VERSION EFUSE_BLK1 128 3
|
||||
169 SYS_DATA_PART2 EFUSE_BLK10 0 256
|
||||
170 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128
|
||||
171 BLK_VERSION_MINOR EFUSE_BLK2 130 3
|
||||
172 BLK_VERSION_MAJOR EFUSE_BLK2 133 2
|
||||
173 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK2 135 1
|
||||
174 TEMP_CALIB EFUSE_BLK2 136 9
|
||||
175 ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK2 145 10
|
||||
176 ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK2 155 10
|
||||
177 ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK2 165 10
|
||||
178 ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK2 175 10
|
||||
179 ADC1_HI_DOUT_ATTEN0 EFUSE_BLK2 185 10
|
||||
180 ADC1_HI_DOUT_ATTEN1 EFUSE_BLK2 195 10
|
||||
181 ADC1_HI_DOUT_ATTEN2 EFUSE_BLK2 205 10
|
||||
182 ADC1_HI_DOUT_ATTEN3 EFUSE_BLK2 215 10
|
||||
183 ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK2 225 4
|
||||
184 ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK2 229 4
|
||||
185 ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK2 233 4
|
||||
186 ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK2 237 4
|
||||
187 ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK2 241 4
|
||||
188 USER_DATA EFUSE_BLK3 0 256
|
||||
189 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48
|
||||
190 KEY0 EFUSE_BLK4 0 256
|
||||
191 KEY1 EFUSE_BLK5 0 256
|
||||
192 KEY2 EFUSE_BLK6 0 256
|
||||
193 KEY3 EFUSE_BLK7 0 256
|
||||
194 KEY4 EFUSE_BLK8 0 256
|
||||
195 KEY5 EFUSE_BLK9 0 256
|
||||
|
||||
Used bits in efuse table:
|
||||
EFUSE_BLK0
|
||||
[0 31] [0 0] [2 2] ... [21 21] [21 22] [22 30] [30 38] [32 122] [124 130] [132 181]
|
||||
|
||||
EFUSE_BLK1
|
||||
[0 99] [114 130]
|
||||
|
||||
EFUSE_BLK10
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK2
|
||||
[0 127] [130 244]
|
||||
|
||||
EFUSE_BLK3
|
||||
[0 255] [200 247]
|
||||
|
||||
EFUSE_BLK4
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK5
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK6
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK7
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK8
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK9
|
||||
[0 255]
|
||||
|
||||
Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
|
||||
|
||||
@@ -1,4 +1,282 @@
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
To be updated
|
||||
$ ./efuse_table_gen.py --idf_target {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info
|
||||
|
||||
Parsing efuse CSV input file esp32h4/esp_efuse_table.csv ...
|
||||
Verifying efuse table...
|
||||
Max number of bits in BLK 256
|
||||
Sorted efuse table:
|
||||
# field_name efuse_block bit_start bit_count
|
||||
1 WR_DIS EFUSE_BLK0 0 32
|
||||
2 WR_DIS.RD_DIS EFUSE_BLK0 0 1
|
||||
3 WR_DIS.KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 1 1
|
||||
4 WR_DIS.KM_RND_SWITCH_CYCLE EFUSE_BLK0 1 1
|
||||
5 WR_DIS.KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 1 1
|
||||
6 WR_DIS.FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 1 1
|
||||
7 WR_DIS.FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 1 1
|
||||
8 WR_DIS.KM_XTS_KEY_LENGTH_256 EFUSE_BLK0 1 1
|
||||
9 WR_DIS.LOCK_KM_KEY EFUSE_BLK0 1 1
|
||||
10 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1
|
||||
11 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1
|
||||
12 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 2 1
|
||||
13 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1
|
||||
14 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1
|
||||
15 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1
|
||||
16 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1
|
||||
17 WR_DIS.PVT_GLITCH_EN EFUSE_BLK0 2 1
|
||||
18 WR_DIS.PVT_GLITCH_MODE EFUSE_BLK0 2 1
|
||||
19 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1
|
||||
20 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1
|
||||
21 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1
|
||||
22 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1
|
||||
23 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1
|
||||
24 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1
|
||||
25 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1
|
||||
26 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1
|
||||
27 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1
|
||||
28 WR_DIS.KEY_PURPOSE_5 EFUSE_BLK0 13 1
|
||||
29 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1
|
||||
30 WR_DIS.XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 14 1
|
||||
31 WR_DIS.XTS_DPA_CLK_ENABLE EFUSE_BLK0 14 1
|
||||
32 WR_DIS.ECC_FORCE_CONST_TIME EFUSE_BLK0 14 1
|
||||
33 WR_DIS.SECURE_BOOT_SHA384_EN EFUSE_BLK0 14 1
|
||||
34 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1
|
||||
35 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1
|
||||
36 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1
|
||||
37 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
38 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1
|
||||
39 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1
|
||||
40 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1
|
||||
41 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1
|
||||
42 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1
|
||||
43 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1
|
||||
44 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1
|
||||
45 WR_DIS.HUK_GEN_STATE EFUSE_BLK0 19 1
|
||||
46 WR_DIS.BLK1 EFUSE_BLK0 20 1
|
||||
47 WR_DIS.MAC EFUSE_BLK0 20 1
|
||||
48 WR_DIS.MAC_EXT EFUSE_BLK0 20 1
|
||||
49 WR_DIS.PVT_LIMIT EFUSE_BLK0 20 1
|
||||
50 WR_DIS.PVT_CELL_SELECT EFUSE_BLK0 20 1
|
||||
51 WR_DIS.PVT_PUMP_LIMIT EFUSE_BLK0 20 1
|
||||
52 WR_DIS.PUMP_DRV EFUSE_BLK0 20 1
|
||||
53 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 20 1
|
||||
54 WR_DIS.HYS_EN_PAD EFUSE_BLK0 20 1
|
||||
55 WR_DIS.PVT_GLITCH_CHARGE_RESET EFUSE_BLK0 20 1
|
||||
56 WR_DIS.VDD_SPI_LDO_ADJUST EFUSE_BLK0 20 1
|
||||
57 WR_DIS.FLASH_LDO_POWER_SEL EFUSE_BLK0 20 1
|
||||
58 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1
|
||||
59 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
60 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
61 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
62 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1
|
||||
63 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 20 1
|
||||
64 WR_DIS.FLASH_CAP EFUSE_BLK0 20 1
|
||||
65 WR_DIS.FLASH_VENDOR EFUSE_BLK0 20 1
|
||||
66 WR_DIS.PSRAM_CAP EFUSE_BLK0 20 1
|
||||
67 WR_DIS.PSRAM_VENDOR EFUSE_BLK0 20 1
|
||||
68 WR_DIS.TEMP EFUSE_BLK0 20 1
|
||||
69 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1
|
||||
70 WR_DIS.PVT_DBIAS EFUSE_BLK0 20 1
|
||||
71 WR_DIS.ADJUST_1V2 EFUSE_BLK0 20 1
|
||||
72 WR_DIS.ADJUST_1V8 EFUSE_BLK0 20 1
|
||||
73 WR_DIS.ACTIVE_DCDC_1V25 EFUSE_BLK0 20 1
|
||||
74 WR_DIS.ACTIVE_DCDC_1V35 EFUSE_BLK0 20 1
|
||||
75 WR_DIS.SLP_DCDC EFUSE_BLK0 20 1
|
||||
76 WR_DIS.LSLP_HP_DRVB EFUSE_BLK0 20 1
|
||||
77 WR_DIS.DSLP_LP_DBIAS EFUSE_BLK0 20 1
|
||||
78 WR_DIS.TEMP_CALIB EFUSE_BLK0 20 1
|
||||
79 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1
|
||||
80 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1
|
||||
81 WR_DIS.OCODE EFUSE_BLK0 21 1
|
||||
82 WR_DIS.DCDC_OCODE EFUSE_BLK0 21 1
|
||||
83 WR_DIS.VDD_3V4_DOUT EFUSE_BLK0 21 1
|
||||
84 WR_DIS.ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK0 21 1
|
||||
85 WR_DIS.ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK0 21 1
|
||||
86 WR_DIS.ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK0 21 1
|
||||
87 WR_DIS.ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK0 21 1
|
||||
88 WR_DIS.ADC1_HI_DOUT_ATTEN0 EFUSE_BLK0 21 1
|
||||
89 WR_DIS.ADC1_HI_DOUT_ATTEN1 EFUSE_BLK0 21 1
|
||||
90 WR_DIS.ADC1_HI_DOUT_ATTEN2 EFUSE_BLK0 21 1
|
||||
91 WR_DIS.ADC1_HI_DOUT_ATTEN3 EFUSE_BLK0 21 1
|
||||
92 WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
93 WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
94 WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
95 WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
96 WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK0 21 1
|
||||
97 WR_DIS.INITCODE_DIFF_1P8_3P3 EFUSE_BLK0 21 1
|
||||
98 WR_DIS.HI_DOUT_DIFF_1P8_3P3 EFUSE_BLK0 21 1
|
||||
99 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1
|
||||
100 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1
|
||||
101 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1
|
||||
102 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1
|
||||
103 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1
|
||||
104 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1
|
||||
105 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1
|
||||
106 WR_DIS.BLOCK_KEY5 EFUSE_BLK0 28 1
|
||||
107 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 29 1
|
||||
108 WR_DIS.USB_EXCHG_PINS EFUSE_BLK0 30 1
|
||||
109 WR_DIS.USB_OTG_FS_EXCHG_PINS EFUSE_BLK0 30 1
|
||||
110 WR_DIS.USB_PHY_SEL EFUSE_BLK0 30 1
|
||||
111 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1
|
||||
112 RD_DIS EFUSE_BLK0 32 7
|
||||
113 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1
|
||||
114 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1
|
||||
115 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1
|
||||
116 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1
|
||||
117 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1
|
||||
118 RD_DIS.BLOCK_KEY5 EFUSE_BLK0 37 1
|
||||
119 RD_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 38 1
|
||||
120 DIS_USB_JTAG EFUSE_BLK0 39 1
|
||||
121 DIS_FORCE_DOWNLOAD EFUSE_BLK0 41 1
|
||||
122 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 42 1
|
||||
123 DIS_TWAI EFUSE_BLK0 43 1
|
||||
124 JTAG_SEL_ENABLE EFUSE_BLK0 44 1
|
||||
125 DIS_PAD_JTAG EFUSE_BLK0 45 1
|
||||
126 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 46 1
|
||||
127 PVT_GLITCH_EN EFUSE_BLK0 50 1
|
||||
128 PVT_GLITCH_MODE EFUSE_BLK0 52 2
|
||||
129 DIS_CORE1 EFUSE_BLK0 54 1
|
||||
130 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 55 3
|
||||
131 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 58 1
|
||||
132 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 59 1
|
||||
133 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 60 1
|
||||
134 KEY_PURPOSE_0 EFUSE_BLK0 64 5
|
||||
135 KEY_PURPOSE_1 EFUSE_BLK0 69 5
|
||||
136 KEY_PURPOSE_2 EFUSE_BLK0 74 5
|
||||
137 KEY_PURPOSE_3 EFUSE_BLK0 79 5
|
||||
138 KEY_PURPOSE_4 EFUSE_BLK0 84 5
|
||||
139 KEY_PURPOSE_5 EFUSE_BLK0 89 5
|
||||
140 SEC_DPA_LEVEL EFUSE_BLK0 94 2
|
||||
141 XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 96 2
|
||||
142 XTS_DPA_CLK_ENABLE EFUSE_BLK0 98 1
|
||||
143 ECC_FORCE_CONST_TIME EFUSE_BLK0 99 1
|
||||
144 SECURE_BOOT_SHA384_EN EFUSE_BLK0 100 1
|
||||
145 SECURE_BOOT_EN EFUSE_BLK0 101 1
|
||||
146 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 102 1
|
||||
147 KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 103 5
|
||||
148 KM_RND_SWITCH_CYCLE EFUSE_BLK0 108 2
|
||||
149 KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 110 5
|
||||
150 FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 115 5
|
||||
151 FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 120 1
|
||||
152 KM_XTS_KEY_LENGTH_256 EFUSE_BLK0 121 1
|
||||
153 LOCK_KM_KEY EFUSE_BLK0 122 1
|
||||
154 FLASH_TPUW EFUSE_BLK0 123 3
|
||||
155 DIS_DOWNLOAD_MODE EFUSE_BLK0 127 1
|
||||
156 DIS_DIRECT_BOOT EFUSE_BLK0 128 1
|
||||
157 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 129 1
|
||||
158 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 130 1
|
||||
159 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 131 1
|
||||
160 UART_PRINT_CONTROL EFUSE_BLK0 132 2
|
||||
161 FORCE_SEND_RESUME EFUSE_BLK0 134 1
|
||||
162 SECURE_VERSION EFUSE_BLK0 135 16
|
||||
163 HUK_GEN_STATE EFUSE_BLK0 151 5
|
||||
164 FLASH_LDO_EFUSE_SEL EFUSE_BLK0 156 1
|
||||
165 USB_EXCHG_PINS EFUSE_BLK0 168 1
|
||||
166 USB_OTG_FS_EXCHG_PINS EFUSE_BLK0 169 1
|
||||
167 USB_PHY_SEL EFUSE_BLK0 170 1
|
||||
168 SOFT_DIS_JTAG EFUSE_BLK0 171 3
|
||||
169 IO_LDO_ADJUST EFUSE_BLK0 174 8
|
||||
170 IO_LDO_1P8 EFUSE_BLK0 182 1
|
||||
171 DCDC_CCM_EN EFUSE_BLK0 183 1
|
||||
172 MAC EFUSE_BLK1 0 8
|
||||
173 MAC EFUSE_BLK1 8 8
|
||||
174 MAC EFUSE_BLK1 16 8
|
||||
175 MAC EFUSE_BLK1 24 8
|
||||
176 MAC EFUSE_BLK1 32 8
|
||||
177 MAC EFUSE_BLK1 40 8
|
||||
178 MAC_EXT EFUSE_BLK1 48 8
|
||||
179 MAC_EXT EFUSE_BLK1 56 8
|
||||
180 PVT_LIMIT EFUSE_BLK1 64 16
|
||||
181 PVT_CELL_SELECT EFUSE_BLK1 80 7
|
||||
182 PVT_PUMP_LIMIT EFUSE_BLK1 87 8
|
||||
183 PUMP_DRV EFUSE_BLK1 96 4
|
||||
184 WDT_DELAY_SEL EFUSE_BLK1 100 2
|
||||
185 HYS_EN_PAD EFUSE_BLK1 102 1
|
||||
186 PVT_GLITCH_CHARGE_RESET EFUSE_BLK1 103 1
|
||||
187 VDD_SPI_LDO_ADJUST EFUSE_BLK1 105 8
|
||||
188 FLASH_LDO_POWER_SEL EFUSE_BLK1 113 1
|
||||
189 WAFER_VERSION_MINOR EFUSE_BLK1 114 4
|
||||
190 WAFER_VERSION_MAJOR EFUSE_BLK1 118 2
|
||||
191 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 120 1
|
||||
192 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK1 121 1
|
||||
193 BLK_VERSION_MINOR EFUSE_BLK1 122 3
|
||||
194 BLK_VERSION_MAJOR EFUSE_BLK1 125 2
|
||||
195 FLASH_CAP EFUSE_BLK1 127 3
|
||||
196 FLASH_VENDOR EFUSE_BLK1 130 3
|
||||
197 PSRAM_CAP EFUSE_BLK1 133 3
|
||||
198 PSRAM_VENDOR EFUSE_BLK1 136 2
|
||||
199 TEMP EFUSE_BLK1 138 2
|
||||
200 PKG_VERSION EFUSE_BLK1 140 3
|
||||
201 PVT_DBIAS EFUSE_BLK1 143 5
|
||||
202 ADJUST_1V2 EFUSE_BLK1 148 4
|
||||
203 ADJUST_1V8 EFUSE_BLK1 152 4
|
||||
204 ACTIVE_DCDC_1V25 EFUSE_BLK1 156 4
|
||||
205 ACTIVE_DCDC_1V35 EFUSE_BLK1 160 4
|
||||
206 SLP_DCDC EFUSE_BLK1 164 5
|
||||
207 LSLP_HP_DRVB EFUSE_BLK1 169 5
|
||||
208 DSLP_LP_DBIAS EFUSE_BLK1 174 2
|
||||
209 TEMP_CALIB EFUSE_BLK1 176 10
|
||||
210 SYS_DATA_PART2 EFUSE_BLK10 0 256
|
||||
211 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128
|
||||
212 OCODE EFUSE_BLK2 128 8
|
||||
213 DCDC_OCODE EFUSE_BLK2 136 8
|
||||
214 VDD_3V4_DOUT EFUSE_BLK2 144 10
|
||||
215 ADC1_AVE_INITCODE_ATTEN0 EFUSE_BLK2 154 9
|
||||
216 ADC1_AVE_INITCODE_ATTEN1 EFUSE_BLK2 163 9
|
||||
217 ADC1_AVE_INITCODE_ATTEN2 EFUSE_BLK2 172 9
|
||||
218 ADC1_AVE_INITCODE_ATTEN3 EFUSE_BLK2 181 9
|
||||
219 ADC1_HI_DOUT_ATTEN0 EFUSE_BLK2 190 9
|
||||
220 ADC1_HI_DOUT_ATTEN1 EFUSE_BLK2 199 9
|
||||
221 ADC1_HI_DOUT_ATTEN2 EFUSE_BLK2 208 9
|
||||
222 ADC1_HI_DOUT_ATTEN3 EFUSE_BLK2 217 9
|
||||
223 ADC1_CH0_ATTEN0_INITCODE_DIFF EFUSE_BLK2 226 3
|
||||
224 ADC1_CH1_ATTEN0_INITCODE_DIFF EFUSE_BLK2 229 3
|
||||
225 ADC1_CH2_ATTEN0_INITCODE_DIFF EFUSE_BLK2 232 3
|
||||
226 ADC1_CH3_ATTEN0_INITCODE_DIFF EFUSE_BLK2 235 3
|
||||
227 ADC1_CH4_ATTEN0_INITCODE_DIFF EFUSE_BLK2 238 3
|
||||
228 INITCODE_DIFF_1P8_3P3 EFUSE_BLK2 241 5
|
||||
229 HI_DOUT_DIFF_1P8_3P3 EFUSE_BLK2 246 5
|
||||
230 USER_DATA EFUSE_BLK3 0 256
|
||||
231 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48
|
||||
232 KEY0 EFUSE_BLK4 0 256
|
||||
233 KEY1 EFUSE_BLK5 0 256
|
||||
234 KEY2 EFUSE_BLK6 0 256
|
||||
235 KEY3 EFUSE_BLK7 0 256
|
||||
236 KEY4 EFUSE_BLK8 0 256
|
||||
237 KEY5 EFUSE_BLK9 0 256
|
||||
|
||||
Used bits in efuse table:
|
||||
EFUSE_BLK0
|
||||
[0 31] [0 1] [1 1] [1 1] [1 1] [1 1] [1 1] [1 2] [2 2] [2 2] [2 2] [2 2] [2 2] [2 2] [2 2] [2 2] [4 14] [14 14] [14 14] [14 14] [14 16] [18 18] [18 18] [18 18] [18 18] [18 18] [18 18] [18 18] [18 18] [18 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 20] [20 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 21] [21 22] [22 30] [30 30] [30 38] [32 39] [41 46] [50 50] [52 60] [64 125] [127 156] [168 183]
|
||||
|
||||
EFUSE_BLK1
|
||||
[0 94] [96 103] [105 185]
|
||||
|
||||
EFUSE_BLK10
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK2
|
||||
[0 250]
|
||||
|
||||
EFUSE_BLK3
|
||||
[0 255] [200 247]
|
||||
|
||||
EFUSE_BLK4
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK5
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK6
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK7
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK8
|
||||
[0 255]
|
||||
|
||||
EFUSE_BLK9
|
||||
[0 255]
|
||||
|
||||
Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
|
||||
|
||||
Reference in New Issue
Block a user