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feat(mspi): support 120MHz flash and psram for esp32c61

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This commit is contained in:
Song Ruo Jing
2026-01-21 14:38:04 +08:00
parent be9b36a201
commit fc4f07abd6
40 changed files with 141 additions and 280 deletions
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components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4 -16
View File
@@ -683,22 +683,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_SPIRAM_SUPPORTED
bool
default y
@@ -1143,6 +1127,10 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool
default y
config SOC_SPI_MEM_FLASH_SUPPORT_HPM
bool
default y
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+2 -4
View File
@@ -288,10 +288,6 @@
// Peripheral supports output given level during its "dummy phase"
#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
/*-------------------------- SPIRAM CAPS ----------------------------------------*/
#define SOC_SPIRAM_SUPPORTED 1
@@ -468,6 +464,8 @@
#define SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)