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feat(mspi): support 120MHz flash and psram for esp32c61

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This commit is contained in:
Song Ruo Jing
2026-01-21 14:38:04 +08:00
parent be9b36a201
commit fc4f07abd6
40 changed files with 141 additions and 280 deletions
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components/soc/esp32/include/soc/Kconfig.soc_caps.in
-16
View File
@@ -511,22 +511,6 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
components/soc/esp32/include/soc/soc_caps.h
-6
View File
@@ -259,12 +259,6 @@
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: DIO, DOUT, QIO, or QOUT
// Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part