From fc18df1aa52b56dd065ffe25661f97e50eaa892d Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Thu, 10 Sep 2026 13:44:28 +0200
Subject: [PATCH] feat(esp_riscv_trace): exclude mask ROM code from trace by
 default

---
 components/esp_riscv_trace/Kconfig            |  9 +++++++
 .../esp_riscv_trace/src/esp_riscv_trace.c     | 27 +++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/components/esp_riscv_trace/Kconfig b/components/esp_riscv_trace/Kconfig
index 9adaf293e16..8370570f629 100644
--- a/components/esp_riscv_trace/Kconfig
+++ b/components/esp_riscv_trace/Kconfig
@@ -247,6 +247,15 @@ menu "RISC-V Trace Encoder Configurations"
             help
                 Maximum number of beats for an undefined-length INCR burst.
 
+        config ESP_RISCV_TRACE_FILTER_OUT_ROM
+            bool "Exclude ROM code from trace"
+            depends on SOC_RISCV_TRACE_FILTER_SUPPORTED
+            default y
+            help
+                Configure the encoder address filter to skip instructions executed in
+                mask ROM. This leaves more buffer space for application trace.
+                Calling esp_riscv_trace_set_filter overrides this setting.
+
     endif # ESP_RISCV_TRACE_ENABLE
 
 endmenu
diff --git a/components/esp_riscv_trace/src/esp_riscv_trace.c b/components/esp_riscv_trace/src/esp_riscv_trace.c
index d0d810f040c..27e5999ddd6 100644
--- a/components/esp_riscv_trace/src/esp_riscv_trace.c
+++ b/components/esp_riscv_trace/src/esp_riscv_trace.c
@@ -19,6 +19,7 @@
 #include "esp_private/startup_internal.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_cpu.h"
+#include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "hal/riscv_trace_hal.h"
 #include "hal/riscv_trace_ll.h"
@@ -171,6 +172,28 @@ static esp_err_t validate_filter_config(const esp_riscv_trace_filter_config_t *c
     }
     return ESP_OK;
 }
+
+/* Configure the encoder filter to skip mask ROM instructions */
+__attribute__((unused))
+static void apply_default_rom_filter(esp_riscv_trace_handle_t handle)
+{
+    riscv_trace_hal_filter_config_t hal_filter = {
+        .enable = true,
+        .match_comparators = true,
+        .primary = {
+            .input = (uint32_t)ESP_RISCV_TRACE_FILTER_INPUT_IADDR,
+            .function = (uint32_t)ESP_RISCV_TRACE_FILTER_COMPARATOR_GE,
+            .match_value = SOC_IROM_MASK_LOW,
+        },
+        .secondary = {
+            .input = (uint32_t)ESP_RISCV_TRACE_FILTER_INPUT_IADDR,
+            .function = (uint32_t)ESP_RISCV_TRACE_FILTER_COMPARATOR_LT,
+            .match_value = SOC_IROM_MASK_HIGH,
+        },
+        .match_mode = (uint32_t)ESP_RISCV_TRACE_FILTER_MODE_NAND,
+    };
+    riscv_trace_hal_set_filter(&handle->hal, &hal_filter);
+}
 #endif // SOC_RISCV_TRACE_FILTER_SUPPORTED
 
 static esp_err_t validate_trace_config(esp_riscv_trace_core_t core_id, const esp_riscv_trace_config_t *config,
@@ -240,6 +263,10 @@ static esp_err_t esp_riscv_trace_new(esp_riscv_trace_core_t core_id, const esp_r
     handle->auto_restart = config->auto_restart;
     *ret_handle = handle;
 
+#if CONFIG_ESP_RISCV_TRACE_FILTER_OUT_ROM
+    apply_default_rom_filter(handle);
+#endif
+
     ESP_EARLY_LOGD(TAG, "RISC-V trace encoder initialized on core %d", core_id);
 
     return ESP_OK;