From fae99eac940ca74a2cd1b8f2b5558986b35a3f40 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Fri, 8 May 2026 14:31:28 +0800 Subject: [PATCH] fix(esp32h4): add pmu modem regs on h4 --- components/soc/esp32h4/register/soc/pmu_reg.h | 438 +++++++++++++++++- 1 file changed, 437 insertions(+), 1 deletion(-) diff --git a/components/soc/esp32h4/register/soc/pmu_reg.h b/components/soc/esp32h4/register/soc/pmu_reg.h index a70cb05a058..96647dbb0ea 100644 --- a/components/soc/esp32h4/register/soc/pmu_reg.h +++ b/components/soc/esp32h4/register/soc/pmu_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -502,6 +502,442 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_XTAL_S 31 +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_MODEM_VDD_FLASH_MODE_M (PMU_HP_MODEM_VDD_FLASH_MODE_V << PMU_HP_MODEM_VDD_FLASH_MODE_S) +#define PMU_HP_MODEM_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_MODEM_VDD_FLASH_MODE_S 18 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_MODEM_DCDC_CCM_ENB_M (PMU_HP_MODEM_DCDC_CCM_ENB_V << PMU_HP_MODEM_DCDC_CCM_ENB_S) +#define PMU_HP_MODEM_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_MODEM_DCDC_CCM_ENB_S 9 +/** PMU_HP_MODEM_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_M (PMU_HP_MODEM_DCDC_CLEAR_RDY_V << PMU_HP_MODEM_DCDC_CLEAR_RDY_S) +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_M (PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V << PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_MODEM_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_HP_MODEM_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_M (PMU_HP_MODEM_DIG_PMU_DSFMOS_V << PMU_HP_MODEM_DIG_PMU_DSFMOS_S) +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_MODEM_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_MODEM_DCM_VSET 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S) +#define PMU_HP_MODEM_DCM_VSET_V 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_S 17 +/** PMU_HP_MODEM_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCM_MODE 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S) +#define PMU_HP_MODEM_DCM_MODE_V 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_S 22 +/** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_TRX (BIT(24)) +#define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S) +#define PMU_HP_MODEM_XPD_TRX_V 0x00000001U +#define PMU_HP_MODEM_XPD_TRX_S 24 +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_M (PMU_HP_MODEM_DISCNNT_DIG_RTC_V << PMU_HP_MODEM_DISCNNT_DIG_RTC_S) +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_S 29 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x0000001FU +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTALX2 (BIT(30)) +#define PMU_HP_MODEM_XPD_XTALX2_M (PMU_HP_MODEM_XPD_XTALX2_V << PMU_HP_MODEM_XPD_XTALX2_S) +#define PMU_HP_MODEM_XPD_XTALX2_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTALX2_S 30 +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + /** PMU_HP_SLEEP_DIG_POWER_REG register * need_des */