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feat(ledc): add support for ESP32S31
This commit is contained in:
Song Ruo Jing
@@ -0,0 +1,929 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for LEDC register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stddef.h>
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#include <stdint.h>
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#include "hal/assert.h"
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#include "hal/ledc_types.h"
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#include "soc/ledc_struct.h"
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#include "soc/ledc_reg.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "soc/hp_system_struct.h"
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#include "soc/soc_caps.h"
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#include "soc/soc_etm_source.h"
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#define LEDC_LL_GET(attr) (LEDC_LL_ ## attr)
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#define LEDC_LL_GET_HW(group_id) ((group_id == 0) ? &LEDC0 : (group_id == 1) ? &LEDC1 : NULL)
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#define LEDC_LL_GROUP_NUM (2)
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#define LEDC_LL_CHANNEL_SUPPORT_OVF_CNT 1
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#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)
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#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)
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#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_RANGE0_SCALE_V)
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#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V)
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#define LEDC_LL_OVF_CNT_MAX (LEDC_OVF_NUM_CH0_V + 1)
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#define LEDC_LL_FRACTIONAL_BITS (8)
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#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
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#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS
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/// Get the mask of the duty change end interrupt status register.
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#define LEDC_LL_DUTY_CHANGE_END_INTR_MASK(speed_mode) (0xffUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
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#define LEDC_LL_EVENT_CHANNEL_DUTY_CHANGE_END(speed_mode, channel) BIT(LEDC_DUTY_CHNG_END_CH0_INT_ENA_S + (channel))
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#define LEDC_LL_EVENT_CHANNEL_OVF_CNT(speed_mode, channel) BIT(LEDC_OVF_CNT_CH0_INT_ENA_S + (channel))
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#define LEDC_LL_EVENT_CHANNEL_MASK(speed_mode, channel) (LEDC_LL_EVENT_CHANNEL_DUTY_CHANGE_END(speed_mode, channel) | LEDC_LL_EVENT_CHANNEL_OVF_CNT(speed_mode, channel))
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// ETM: LEDC1 vs LEDC0 uses a fixed task/event index step and identical MMIO layout at +reg stride.
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#define LEDC_LL_ETM_TASK_ID_GROUP_OFS (LEDC1_TASK_DUTY_SCALE_UPDATE_CH0 - LEDC0_TASK_DUTY_SCALE_UPDATE_CH0)
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#define LEDC_LL_ETM_EVENT_ID_GROUP_OFS (LEDC1_EVT_DUTY_CHNG_END_CH0 - LEDC0_EVT_DUTY_CHNG_END_CH0)
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#define LEDC_LL_ETM_REG_GROUP_OFS (DR_REG_LEDC1_BASE - DR_REG_LEDC0_BASE)
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// Channel tasks: ID, enable register and bit
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#define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
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((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
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[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = LEDC0_TASK_DUTY_SCALE_UPDATE_CH0, \
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[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = LEDC0_TASK_SIG_OUT_DIS_CH0, \
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[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = LEDC0_TASK_OVF_CNT_RST_CH0, \
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[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = LEDC0_TASK_GAMMA_RESTART_CH0, \
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[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = LEDC0_TASK_GAMMA_PAUSE_CH0, \
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[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = LEDC0_TASK_GAMMA_RESUME_CH0, \
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}}[0][(task)] + (channel) + (uint32_t)(group) * LEDC_LL_ETM_TASK_ID_GROUP_OFS)
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#define LEDC_LL_ETM_CHANNEL_TASK_EN_REG(group, task) \
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((volatile uint32_t *)((uintptr_t)((volatile uint32_t *[1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
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[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG(0), \
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[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG(0), \
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[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG(0), \
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[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG(0), \
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[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG(0), \
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[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN2_REG(0), \
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}}[0][(task)]) + (uintptr_t)(group) * LEDC_LL_ETM_REG_GROUP_OFS))
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#define LEDC_LL_ETM_CHANNEL_TASK_EN_BIT(group, channel, task) \
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((uint32_t [1][LEDC_CHANNEL_ETM_TASK_MAX]){{ \
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[LEDC_CHANNEL_ETM_TASK_FADE_SCALE_UPDATE] = BIT(LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S), \
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[LEDC_CHANNEL_ETM_TASK_SIG_OUT_DIS] = BIT(LEDC_TASK_SIG_OUT_DIS_CH0_EN_S), \
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[LEDC_CHANNEL_ETM_TASK_OVF_CNT_RST] = BIT(LEDC_TASK_OVF_CNT_RST_CH0_EN_S), \
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[LEDC_CHANNEL_ETM_TASK_FADE_RESTART] = BIT(LEDC_TASK_GAMMA_RESTART_CH0_EN_S), \
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[LEDC_CHANNEL_ETM_TASK_FADE_PAUSE] = BIT(LEDC_TASK_GAMMA_PAUSE_CH0_EN_S), \
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[LEDC_CHANNEL_ETM_TASK_FADE_RESUME] = BIT(LEDC_TASK_GAMMA_RESUME_CH0_EN_S), \
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}}[0][(task)] << (channel))
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// Channel events: ID, enable register and bit
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#define LEDC_LL_ETM_CHANNEL_EVENT_ID(group, channel, event) \
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((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
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[LEDC_CHANNEL_ETM_EVENT_FADE_END] = LEDC0_EVT_DUTY_CHNG_END_CH0, \
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[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = LEDC0_EVT_OVF_CNT_PLS_CH0, \
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}}[0][(event)] + (channel) + (uint32_t)(group) * LEDC_LL_ETM_EVENT_ID_GROUP_OFS)
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#define LEDC_LL_ETM_CHANNEL_EVENT_EN_REG(group, event) \
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((volatile uint32_t *)((uintptr_t)((volatile uint32_t *[1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
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[LEDC_CHANNEL_ETM_EVENT_FADE_END] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG(0), \
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[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG(0), \
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}}[0][(event)]) + (uintptr_t)(group) * LEDC_LL_ETM_REG_GROUP_OFS))
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#define LEDC_LL_ETM_CHANNEL_EVENT_EN_BIT(group, channel, event) \
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((uint32_t [1][LEDC_CHANNEL_ETM_EVENT_MAX]){{ \
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[LEDC_CHANNEL_ETM_EVENT_FADE_END] = BIT(LEDC_EVT_DUTY_CHNG_END_CH0_EN_S), \
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[LEDC_CHANNEL_ETM_EVENT_REACH_MAX_OVF_CNT] = BIT(LEDC_EVT_OVF_CNT_PLS_CH0_EN_S), \
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}}[0][(event)] << (channel))
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// Timer tasks: ID, enable register and bit
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#define LEDC_LL_ETM_TIMER_TASK_ID(group, timer, task) \
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((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
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[LEDC_TIMER_ETM_TASK_RST] = LEDC0_TASK_TIMER0_RST, \
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[LEDC_TIMER_ETM_TASK_RESUME] = LEDC0_TASK_TIMER0_RESUME, \
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[LEDC_TIMER_ETM_TASK_PAUSE] = LEDC0_TASK_TIMER0_PAUSE, \
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}}[0][(task)] + (timer) + (uint32_t)(group) * LEDC_LL_ETM_TASK_ID_GROUP_OFS)
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#define LEDC_LL_ETM_TIMER_TASK_EN_REG(group, task) \
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((volatile uint32_t *)((uintptr_t)((volatile uint32_t *[1][LEDC_TIMER_ETM_TASK_MAX]){{ \
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[LEDC_TIMER_ETM_TASK_RST] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG(0), \
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[LEDC_TIMER_ETM_TASK_RESUME] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG(0), \
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[LEDC_TIMER_ETM_TASK_PAUSE] = (volatile uint32_t *)LEDC_EVT_TASK_EN1_REG(0), \
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}}[0][(task)]) + (uintptr_t)(group) * LEDC_LL_ETM_REG_GROUP_OFS))
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#define LEDC_LL_ETM_TIMER_TASK_EN_BIT(group, timer, task) \
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((uint32_t [1][LEDC_TIMER_ETM_TASK_MAX]){{ \
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[LEDC_TIMER_ETM_TASK_RST] = BIT(LEDC_TASK_TIMER0_RST_EN_S), \
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[LEDC_TIMER_ETM_TASK_RESUME] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
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[LEDC_TIMER_ETM_TASK_PAUSE] = BIT(LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S), \
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}}[0][(task)] << (timer))
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// Timer events: ID, enable register and bit
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#define LEDC_LL_ETM_TIMER_EVENT_ID(group, timer, event) \
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((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
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[LEDC_TIMER_ETM_EVENT_OVF] = LEDC0_EVT_TIME_OVF_TIMER0, \
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}}[0][(event)] + (timer) + (uint32_t)(group) * LEDC_LL_ETM_EVENT_ID_GROUP_OFS)
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#define LEDC_LL_ETM_TIMER_EVENT_EN_REG(group, event) \
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((volatile uint32_t *)((uintptr_t)((volatile uint32_t *[1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
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[LEDC_TIMER_ETM_EVENT_OVF] = (volatile uint32_t *)LEDC_EVT_TASK_EN0_REG(0), \
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}}[0][(event)]) + (uintptr_t)(group) * LEDC_LL_ETM_REG_GROUP_OFS))
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#define LEDC_LL_ETM_TIMER_EVENT_EN_BIT(group, timer, event) \
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((uint32_t [1][LEDC_TIMER_ETM_EVENT_MAX]){{ \
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[LEDC_TIMER_ETM_EVENT_OVF] = BIT(LEDC_EVT_TIME_OVF_TIMER0_EN_S), \
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}}[0][(event)] << (timer))
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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LEDC_LL_MEM_LP_MODE_DEEP_SLEEP, // memory will enter deep sleep during low power stage, keep memory data
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LEDC_LL_MEM_LP_MODE_LIGHT_SLEEP, // memory will enter light sleep during low power stage, keep memory data
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LEDC_LL_MEM_LP_MODE_SHUT_DOWN, // memory will be powered down during low power stage
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LEDC_LL_MEM_LP_MODE_DISABLE, // disable the low power stage
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} ledc_ll_mem_lp_mode_t;
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/**
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* @brief Enable peripheral register clock
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*
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* @param group_id LEDC group ID
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* @param enable Enable/Disable
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*/
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static inline void ledc_ll_enable_bus_clock(int group_id, bool enable)
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{
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switch (group_id) {
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case 0:
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc0_apb_clk_en = enable;
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break;
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case 1:
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc1_apb_clk_en = enable;
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break;
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default:
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abort();
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break;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ledc_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ledc_ll_enable_bus_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Reset whole peripheral register to init value defined by HW design
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*
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* @param group_id LEDC group ID
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*/
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static inline void ledc_ll_reset_register(int group_id)
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{
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switch (group_id) {
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case 0:
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc0_rst_en = 1;
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc0_rst_en = 0;
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break;
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case 1:
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc1_rst_en = 1;
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc1_rst_en = 0;
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break;
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default:
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abort();
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break;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ledc_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ledc_ll_reset_register(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Force power on the LEDC memory block, regardless of the outside PMU logic
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*
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* @param dev Peripheral instance address
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*/
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static inline void ledc_ll_mem_force_power_on(ledc_dev_t *dev)
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{
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if (dev == &LEDC0) {
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_force_ctrl = 1;
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_lp_en = 0;
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} else if (dev == &LEDC1) {
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_force_ctrl = 1;
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_lp_en = 0;
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} else {
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abort();
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}
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}
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/**
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* @brief Force the LEDC memory block into low power mode, regardless of the outside PMU logic
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*
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* @param dev Peripheral instance address
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*/
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static inline void ledc_ll_mem_force_low_power(ledc_dev_t *dev)
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{
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if (dev == &LEDC0) {
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_force_ctrl = 1;
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_lp_en = 1;
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} else if (dev == &LEDC1) {
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_force_ctrl = 1;
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_lp_en = 1;
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} else {
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abort();
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}
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}
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/**
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* @brief Power control the LEDC memory block by the outside PMU logic
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*
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* @param dev Peripheral instance address
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*/
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static inline void ledc_ll_mem_power_by_pmu(ledc_dev_t *dev)
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{
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if (dev == &LEDC0) {
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_force_ctrl = 0;
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_lp_en = 0;
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} else if (dev == &LEDC1) {
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_force_ctrl = 0;
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_lp_en = 0;
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} else {
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abort();
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}
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}
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/**
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* @brief Set low power mode for LEDC memory block
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*
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* @param dev Peripheral instance address
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* @param mode LEDC memory low power mode in low power stage
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*/
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static inline void ledc_ll_mem_set_low_power_mode(ledc_dev_t *dev, ledc_ll_mem_lp_mode_t mode)
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{
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if (dev == &LEDC0) {
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HP_SYSTEM.sys_ledc0_mem_lp_ctrl.sys_ledc0_mem_lp_mode = mode;
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} else if (dev == &LEDC1) {
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HP_SYSTEM.sys_ledc1_mem_lp_ctrl.sys_ledc1_mem_lp_mode = mode;
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} else {
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abort();
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}
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}
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/**
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* @brief Enable LEDC function clock
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*
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* @param group_id LEDC group ID
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* @param en True to enable, false to disable
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*
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* @return None
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*/
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static inline void ledc_ll_enable_clock(int group_id, bool en)
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{
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switch (group_id) {
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case 0:
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc0_clk_en = en;
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break;
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case 1:
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HP_SYS_CLKRST.ledc_ctrl0.reg_ledc1_clk_en = en;
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break;
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default:
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abort();
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break;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ledc_ll_enable_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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ledc_ll_enable_clock(__VA_ARGS__); \
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} while(0)
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/**
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* @brief Enable the power for LEDC channel
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*
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* @param hw Beginning address of the peripheral registers
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* @param speed_mode LEDC speed_mode, low-speed mode only
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* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
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* @param en True to enable, false to disable
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*/
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static inline void ledc_ll_enable_channel_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool en)
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{
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if (en) {
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hw->ch_power_up_conf.val |= BIT(speed_mode * SOC_LEDC_CHANNEL_NUM + channel_num);
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} else {
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hw->ch_power_up_conf.val &= ~BIT(speed_mode * SOC_LEDC_CHANNEL_NUM + channel_num);
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}
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}
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/**
|
||||
* @brief Enable the power for LEDC timer
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param en True to enable, false to disable
|
||||
*/
|
||||
static inline void ledc_ll_enable_timer_power(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, bool en)
|
||||
{
|
||||
if (en) {
|
||||
hw->timer_power_up_conf.val |= BIT(speed_mode * SOC_LEDC_TIMER_NUM + timer_sel);
|
||||
} else {
|
||||
hw->timer_power_up_conf.val &= ~BIT(speed_mode * SOC_LEDC_TIMER_NUM + timer_sel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC low speed timer clock
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param slow_clk_sel LEDC low speed timer clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel)
|
||||
{
|
||||
uint32_t clk_sel_val = 3;
|
||||
switch (slow_clk_sel) {
|
||||
case LEDC_SLOW_CLK_XTAL:
|
||||
clk_sel_val = 0;
|
||||
break;
|
||||
case LEDC_SLOW_CLK_RC_FAST:
|
||||
clk_sel_val = 1;
|
||||
break;
|
||||
case LEDC_SLOW_CLK_PLL_DIV:
|
||||
clk_sel_val = 2;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
break;
|
||||
}
|
||||
|
||||
if (hw == &LEDC0) {
|
||||
HP_SYS_CLKRST.ledc_ctrl0.reg_ledc0_clk_src_sel = clk_sel_val;
|
||||
} else if (hw == &LEDC1) {
|
||||
HP_SYS_CLKRST.ledc_ctrl0.reg_ledc1_clk_src_sel = clk_sel_val;
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define ledc_ll_set_slow_clk_sel(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
ledc_ll_set_slow_clk_sel(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Get LEDC low speed timer clock
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param slow_clk_sel LEDC low speed timer clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel)
|
||||
{
|
||||
uint32_t clk_sel_val = 3;
|
||||
if (hw == &LEDC0) {
|
||||
clk_sel_val = HP_SYS_CLKRST.ledc_ctrl0.reg_ledc0_clk_src_sel;
|
||||
} else if (hw == &LEDC1) {
|
||||
clk_sel_val = HP_SYS_CLKRST.ledc_ctrl0.reg_ledc1_clk_src_sel;
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
|
||||
switch (clk_sel_val) {
|
||||
case 0:
|
||||
*slow_clk_sel = LEDC_SLOW_CLK_XTAL;
|
||||
break;
|
||||
case 1:
|
||||
*slow_clk_sel = LEDC_SLOW_CLK_RC_FAST;
|
||||
break;
|
||||
case 2:
|
||||
*slow_clk_sel = LEDC_SLOW_CLK_PLL_DIV;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update LEDC low speed timer
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
|
||||
{
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.para_up = 1;
|
||||
// Here, we don't wait for the bit gets cleared since it can take quite long depends on the pwm frequency
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset LEDC timer
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
|
||||
{
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Pause LEDC timer
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
|
||||
{
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume LEDC timer
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
|
||||
{
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC timer clock divider
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider)
|
||||
{
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div = clock_divider;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC timer clock divider
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider)
|
||||
{
|
||||
*clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC timer clock source
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param clk_src Pointer to accept the timer clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
|
||||
{
|
||||
// The target has no timer-specific clock source option
|
||||
*clk_src = LEDC_SCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC duty resolution
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)]
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution)
|
||||
{
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC duty resolution
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param duty_resolution Pointer to accept the resolution of duty setting in number of bits.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution)
|
||||
{
|
||||
*duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC max duty
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param max_duty Pointer to accept the max duty
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty)
|
||||
{
|
||||
*max_duty = (1 << (hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update channel configure when select low speed mode
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].conf0.para_up = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC hpoint value
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param hpoint_val LEDC hpoint value(max: 0xfffff)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC hpoint value
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val)
|
||||
{
|
||||
*hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC the integer part of duty value
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)]
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].duty_init.duty = duty_val << 4;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC duty value
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param duty_val Pointer to accept the LEDC duty value
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val)
|
||||
{
|
||||
*duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to set fade parameters all-in-one
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
|
||||
* @param dir LEDC duty change direction, increase or decrease
|
||||
* @param cycle The duty cycles
|
||||
* @param scale The step scale
|
||||
* @param step The number of increased or decreased times
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
|
||||
{
|
||||
HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX);
|
||||
ledc_channel_gamma_fade_param_t range_param = {};
|
||||
range_param.duty_inc = dir;
|
||||
range_param.duty_cycle = cycle;
|
||||
range_param.scale = scale;
|
||||
range_param.duty_num = step;
|
||||
if (hw == &LEDC0) {
|
||||
LEDC0_GAMMA_RAM.channel[channel_num].entry[range].val = range_param.val;
|
||||
} else if (hw == &LEDC1) {
|
||||
LEDC1_GAMMA_RAM.channel[channel_num].entry[range].val = range_param.val;
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the total number of ranges in one fading
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param range_num Total number of ranges (1 - SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX) of the fading configured
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num)
|
||||
{
|
||||
hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num = range_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the total number of ranges in one fading
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param range_num Pointer to accept fade range number
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num)
|
||||
{
|
||||
*range_num = hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get fade configurations in gamma_rd register
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
|
||||
* @param dir Pointer to accept fade direction value
|
||||
* @param cycle Pointer to accept fade cycle value
|
||||
* @param scale Pointer to accept fade scale value
|
||||
* @param step Pointer to accept fade step value
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
|
||||
{
|
||||
ledc_channel_gamma_fade_param_t range_param = {
|
||||
.val = (hw == &LEDC0) ? LEDC0_GAMMA_RAM.channel[channel_num].entry[range].val :
|
||||
(hw == &LEDC1) ? LEDC1_GAMMA_RAM.channel[channel_num].entry[range].val : 0,
|
||||
};
|
||||
|
||||
*dir = range_param.duty_inc;
|
||||
*cycle = range_param.duty_cycle;
|
||||
*scale = range_param.scale;
|
||||
*step = range_param.duty_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the output enable
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param sig_out_en The output enable status
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the duty start
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set output idle level
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param idle_level The output idle level
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LEDC interrupt for specific event mask
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param mask Interrupt enable mask
|
||||
* @param enable True to enable, False to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ledc_ll_enable_interrupt(ledc_dev_t *hw, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
hw->int_ena.val |= mask;
|
||||
} else {
|
||||
hw->int_ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
*
|
||||
* @return Interrupt status.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t ledc_ll_get_intr_status(ledc_dev_t *hw)
|
||||
{
|
||||
return hw->int_st.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the address of the interrupt status register.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @return Pointer to the interrupt status register.
|
||||
*/
|
||||
static inline volatile void* ledc_ll_get_intr_status_reg(ledc_dev_t *hw)
|
||||
{
|
||||
return (volatile void *)&hw->int_st;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt status.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param intr_mask Interrupt status mask to clear
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ledc_ll_clear_intr_status(ledc_dev_t *hw, uint32_t intr_mask)
|
||||
{
|
||||
hw->int_clr.val = intr_mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set timer index of the specified channel
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get timer index of the specified channel
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param timer_sel Pointer to accept the LEDC timer index
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
|
||||
{
|
||||
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable ETM event/task
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param reg_addr Register address to control the ETM event/task
|
||||
* @param bit Bit position in the register
|
||||
* @param enable Enable or disable the ETM event/task
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_etm_enable_evt_task(ledc_dev_t *hw, ledc_mode_t speed_mode, volatile uint32_t *reg_addr, uint32_t bit, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
REG_SET_BIT(reg_addr, bit);
|
||||
} else {
|
||||
REG_CLR_BIT(reg_addr, bit);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the timer overflow counter for the specified channel
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param enable True to enable; false to disable
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_channel_enable_timer_ovt_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, bool enable)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the maximum timer overflow count for the specified channel
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel LEDC channel index (0-7), select from ledc_channel_t
|
||||
* @param max_ovf_cnt The maximum timer overflow count
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_channel_set_maximum_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t max_ovf_cnt)
|
||||
{
|
||||
HAL_ASSERT(max_ovf_cnt > 0 && max_ovf_cnt <= LEDC_LL_OVF_CNT_MAX);
|
||||
hw->channel_group[speed_mode].channel[channel].conf0.ovf_num = max_ovf_cnt - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the timer overflow counter for the specified channel
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, low-speed mode only
|
||||
* @param channel LEDC channel index (0-7), select from ledc_channel_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_channel_reset_timer_ovf_cnt(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel)
|
||||
{
|
||||
hw->channel_group[speed_mode].channel[channel].conf0.ovf_cnt_reset = 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,284 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "hal/ledc_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/ledc_reg.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every LEDC peripheral: GPIO signals
|
||||
*/
|
||||
const ledc_signal_conn_t ledc_periph_signal[2] = {
|
||||
{
|
||||
.irq_id = ETS_LEDC0_INTR_SOURCE,
|
||||
.speed_mode = {
|
||||
[0] = {
|
||||
.sig_out_idx = {
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT0_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT1_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT2_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT3_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT4_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT5_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT6_IDX,
|
||||
LEDC0_LS_SIG_OUT_PAD_OUT7_IDX,
|
||||
}
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
.irq_id = ETS_LEDC1_INTR_SOURCE,
|
||||
.speed_mode = {
|
||||
[0] = {
|
||||
.sig_out_idx = {
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT0_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT1_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT2_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT3_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT4_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT5_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT6_IDX,
|
||||
LEDC1_LS_SIG_OUT_PAD_OUT7_IDX,
|
||||
}
|
||||
},
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* LEDC registers to be saved for sleep retention
|
||||
*
|
||||
* channel:
|
||||
* LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
|
||||
* LEDC_CHx_GAMMA_CONF_REG, LEDC_CHx_GAMMA_RANGEi_REG
|
||||
*
|
||||
* timer:
|
||||
* LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
|
||||
*
|
||||
* common:
|
||||
* LEDC_INT_ENA_REG,
|
||||
* LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
|
||||
* LEDC_CONF_REG,
|
||||
* LEDC_CH_POWER_UP_CONF_REG, LEDC_TIMER_POWER_UP_CONF_REG
|
||||
*
|
||||
* Note 1: Gamma parameter registers are backuped and restored. But we won't start a fade automatically after wake-up.
|
||||
* Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
|
||||
*
|
||||
* Note 2: For timer/channel registers to get synced, update bits need to be set
|
||||
*
|
||||
* Note 3: Gamma RAM registers R/W relies both APB and function clock, therefore, retention requires the existence of function clock
|
||||
*/
|
||||
#define LEDC_COMMON_RETENTION_REGS_CNT 7
|
||||
#define LEDC_COMMON_RETENTION_REGS_BASE(i) (DR_REG_LEDC_BASE(i) + 0xc8)
|
||||
static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x1c00, 0x0, 0x0};
|
||||
// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
|
||||
// Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
|
||||
#define LEDC_COMMON_RETENTION_ENTRIES(i) { \
|
||||
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00), \
|
||||
LEDC_INT_ENA_REG(i), 0, \
|
||||
(LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01), \
|
||||
LEDC_COMMON_RETENTION_REGS_BASE(i), LEDC_COMMON_RETENTION_REGS_BASE(i), \
|
||||
LEDC_COMMON_RETENTION_REGS_CNT, 0, 0, \
|
||||
ledc_common_regs_map[0], ledc_common_regs_map[1], \
|
||||
ledc_common_regs_map[2], ledc_common_regs_map[3]), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
}
|
||||
|
||||
#define LEDC_TIMER_RETENTION_ENTRIES(i, timer) { \
|
||||
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
|
||||
LEDC_TIMER##timer##_CONF_REG(i), LEDC_TIMER##timer##_CONF_REG(i), \
|
||||
1, 0, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
|
||||
LEDC_TIMER##timer##_CMP_REG(i), LEDC_TIMER##timer##_CMP_REG(i), \
|
||||
1, 0, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
|
||||
LEDC_TIMER##timer##_CONF_REG(i), LEDC_TIMER##timer##_PARA_UP, \
|
||||
LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
}
|
||||
|
||||
#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
|
||||
static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
|
||||
static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0};
|
||||
#define LEDC_CHANNEL_RETENTION_ENTRIES(i, chan) { \
|
||||
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
|
||||
LEDC_CH##chan##_CONF0_REG(i), LEDC_CH##chan##_CONF0_REG(i), \
|
||||
LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
|
||||
ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
|
||||
ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
|
||||
LEDC_CH##chan##_DUTY_R_REG(i), LEDC_CH##chan##_DUTY_REG(i), \
|
||||
1, 0, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
|
||||
LEDC_CH##chan##_CONF1_REG(i), LEDC_DUTY_START_CH##chan, \
|
||||
LEDC_DUTY_START_CH##chan##_M, 1, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
|
||||
LEDC_CH##chan##_CONF0_REG(i), LEDC_PARA_UP_CH##chan, \
|
||||
LEDC_PARA_UP_CH##chan##_M, 1, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \
|
||||
LEDC_CH##chan##_GAMMA_CONF_REG(i), LEDC_CH##chan##_GAMMA_CONF_REG(i), \
|
||||
1, 0, 0), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
[5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \
|
||||
LEDC_CH##chan##_GAMMA_RANGE0_REG(i), LEDC_CH##chan##_GAMMA_RANGE0_REG(i), \
|
||||
SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX, 0, 0, \
|
||||
ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \
|
||||
ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \
|
||||
.owner = LEDC_RETENTION_ENTRY }, \
|
||||
}
|
||||
|
||||
static const regdma_entries_config_t ledc0_common_regdma_entries[] = LEDC_COMMON_RETENTION_ENTRIES(0);
|
||||
|
||||
static const regdma_entries_config_t ledc0_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0, 0);
|
||||
static const regdma_entries_config_t ledc0_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0, 1);
|
||||
static const regdma_entries_config_t ledc0_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0, 2);
|
||||
static const regdma_entries_config_t ledc0_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0, 3);
|
||||
|
||||
static const regdma_entries_config_t ledc0_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 0);
|
||||
static const regdma_entries_config_t ledc0_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 1);
|
||||
static const regdma_entries_config_t ledc0_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 2);
|
||||
static const regdma_entries_config_t ledc0_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 3);
|
||||
static const regdma_entries_config_t ledc0_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 4);
|
||||
static const regdma_entries_config_t ledc0_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 5);
|
||||
static const regdma_entries_config_t ledc0_channel6_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 6);
|
||||
static const regdma_entries_config_t ledc0_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0, 7);
|
||||
|
||||
static const regdma_entries_config_t ledc1_common_regdma_entries[] = LEDC_COMMON_RETENTION_ENTRIES(1);
|
||||
|
||||
static const regdma_entries_config_t ledc1_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1, 0);
|
||||
static const regdma_entries_config_t ledc1_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1, 1);
|
||||
static const regdma_entries_config_t ledc1_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1, 2);
|
||||
static const regdma_entries_config_t ledc1_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1, 3);
|
||||
|
||||
static const regdma_entries_config_t ledc1_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 0);
|
||||
static const regdma_entries_config_t ledc1_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 1);
|
||||
static const regdma_entries_config_t ledc1_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 2);
|
||||
static const regdma_entries_config_t ledc1_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 3);
|
||||
static const regdma_entries_config_t ledc1_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 4);
|
||||
static const regdma_entries_config_t ledc1_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 5);
|
||||
static const regdma_entries_config_t ledc1_channel6_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 6);
|
||||
static const regdma_entries_config_t ledc1_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1, 7);
|
||||
|
||||
const ledc_reg_retention_info_t ledc_reg_retention_info[2] = {
|
||||
{
|
||||
.common = {
|
||||
.regdma_entry_array = ledc0_common_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_common_regdma_entries),
|
||||
},
|
||||
.timer[0] = {
|
||||
.regdma_entry_array = ledc0_timer0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_timer0_regdma_entries),
|
||||
},
|
||||
.timer[1] = {
|
||||
.regdma_entry_array = ledc0_timer1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_timer1_regdma_entries),
|
||||
},
|
||||
.timer[2] = {
|
||||
.regdma_entry_array = ledc0_timer2_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_timer2_regdma_entries),
|
||||
},
|
||||
.timer[3] = {
|
||||
.regdma_entry_array = ledc0_timer3_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_timer3_regdma_entries),
|
||||
},
|
||||
.channel[0] = {
|
||||
.regdma_entry_array = ledc0_channel0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel0_regdma_entries),
|
||||
},
|
||||
.channel[1] = {
|
||||
.regdma_entry_array = ledc0_channel1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel1_regdma_entries),
|
||||
},
|
||||
.channel[2] = {
|
||||
.regdma_entry_array = ledc0_channel2_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel2_regdma_entries),
|
||||
},
|
||||
.channel[3] = {
|
||||
.regdma_entry_array = ledc0_channel3_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel3_regdma_entries),
|
||||
},
|
||||
.channel[4] = {
|
||||
.regdma_entry_array = ledc0_channel4_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel4_regdma_entries),
|
||||
},
|
||||
.channel[5] = {
|
||||
.regdma_entry_array = ledc0_channel5_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel5_regdma_entries),
|
||||
},
|
||||
.channel[6] = {
|
||||
.regdma_entry_array = ledc0_channel6_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel6_regdma_entries),
|
||||
},
|
||||
.channel[7] = {
|
||||
.regdma_entry_array = ledc0_channel7_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc0_channel7_regdma_entries),
|
||||
},
|
||||
.module_id = SLEEP_RETENTION_MODULE_LEDC0,
|
||||
},
|
||||
{
|
||||
.common = {
|
||||
.regdma_entry_array = ledc1_common_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_common_regdma_entries),
|
||||
},
|
||||
.timer[0] = {
|
||||
.regdma_entry_array = ledc1_timer0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_timer0_regdma_entries),
|
||||
},
|
||||
.timer[1] = {
|
||||
.regdma_entry_array = ledc1_timer1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_timer1_regdma_entries),
|
||||
},
|
||||
.timer[2] = {
|
||||
.regdma_entry_array = ledc1_timer2_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_timer2_regdma_entries),
|
||||
},
|
||||
.timer[3] = {
|
||||
.regdma_entry_array = ledc1_timer3_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_timer3_regdma_entries),
|
||||
},
|
||||
.channel[0] = {
|
||||
.regdma_entry_array = ledc1_channel0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel0_regdma_entries),
|
||||
},
|
||||
.channel[1] = {
|
||||
.regdma_entry_array = ledc1_channel1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel1_regdma_entries),
|
||||
},
|
||||
.channel[2] = {
|
||||
.regdma_entry_array = ledc1_channel2_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel2_regdma_entries),
|
||||
},
|
||||
.channel[3] = {
|
||||
.regdma_entry_array = ledc1_channel3_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel3_regdma_entries),
|
||||
},
|
||||
.channel[4] = {
|
||||
.regdma_entry_array = ledc1_channel4_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel4_regdma_entries),
|
||||
},
|
||||
.channel[5] = {
|
||||
.regdma_entry_array = ledc1_channel5_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel5_regdma_entries),
|
||||
},
|
||||
.channel[6] = {
|
||||
.regdma_entry_array = ledc1_channel6_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel6_regdma_entries),
|
||||
},
|
||||
.channel[7] = {
|
||||
.regdma_entry_array = ledc1_channel7_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(ledc1_channel7_regdma_entries),
|
||||
},
|
||||
.module_id = SLEEP_RETENTION_MODULE_LEDC1,
|
||||
},
|
||||
};
|
||||
Reference in New Issue
Block a user