diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c index 04d7e018a05..d0f759c3ab3 100644 --- a/components/bootloader_support/src/bootloader_efuse.c +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -42,7 +42,6 @@ int bootloader_clock_get_rated_freq_mhz(void) return 96; #elif CONFIG_IDF_TARGET_ESP32H21 - //TODO: [ESP32H21] IDF-11556, please check return 96; #elif CONFIG_IDF_TARGET_ESP32H4 diff --git a/components/efuse/esp32h21/esp_efuse_table.c b/components/efuse/esp32h21/esp_efuse_table.c index 2aa510ada0e..ebb63221809 100644 --- a/components/efuse/esp32h21/esp_efuse_table.c +++ b/components/efuse/esp32h21/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 4ec5511e3b738f65373b56d5cdecea93 +// md5_digest_table d2954679788e8cfb56ac5273aa5ed838 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -23,6 +23,10 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; +static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_EN[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PVT_GLITCH_EN, +}; + static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; @@ -44,7 +48,7 @@ static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { }; static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { - {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI, }; static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { @@ -59,6 +63,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, }; +static const esp_efuse_desc_t WR_DIS_POWERGLITCH_EN1[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of POWERGLITCH_EN1, +}; + static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, }; @@ -103,6 +111,10 @@ static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, }; +static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL, +}; + static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, }; @@ -140,7 +152,7 @@ static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { }; static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, }; static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { @@ -187,32 +199,52 @@ static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, }; -static const esp_efuse_desc_t WR_DIS_RXIQ_VERSION[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_VERSION, +static const esp_efuse_desc_t WR_DIS_PVT_CELL_SELECT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_CELL_SELECT, }; -static const esp_efuse_desc_t WR_DIS_RXIQ_0[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_0, +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, }; -static const esp_efuse_desc_t WR_DIS_RXIQ_1[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_1, +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, +static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, }; -static const esp_efuse_desc_t WR_DIS_DSLP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_DBIAS, +static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, }; -static const esp_efuse_desc_t WR_DIS_DBIAS_VOL_GAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DBIAS_VOL_GAP, +static const esp_efuse_desc_t WR_DIS_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_LIMIT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_LIMIT, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_CHARGE_RESET[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_GLITCH_CHARGE_RESET, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_MODE[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_GLITCH_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_PUMP_LIMIT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_PUMP_LIMIT, +}; + +static const esp_efuse_desc_t WR_DIS_PUMP_DRV[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PUMP_DRV, }; static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { @@ -227,18 +259,6 @@ static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, -}; - static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, }; @@ -251,74 +271,6 @@ static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF, -}; - static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, }; @@ -400,79 +352,67 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { }; static const esp_efuse_desc_t PVT_GLITCH_EN[] = { - {EFUSE_BLK0, 39, 1}, // [] Represents whether pvt glitch is enabled, + {EFUSE_BLK0, 39, 1}, // [] Represents whether to enable PVT power glitch monitor function.1: Enable. 0: Disable, }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled, + {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled or enabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 41, 1}, // [] Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t POWERGLITCH_EN[] = { - {EFUSE_BLK0, 42, 1}, // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled, -}; - -static const esp_efuse_desc_t DIS_USJ[] = { - {EFUSE_BLK0, 43, 1}, // [] Represents whether usb serial jtag is disabled, + {EFUSE_BLK0, 42, 1}, // [] Represents whether to enable power glitch function., }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into Download mode is disabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 45, 1}, // [] Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during boot_mode_download. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t DIS_TWAI[] = { - {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI function is disabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0, + {EFUSE_BLK0, 47, 1}, // [] Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured to 0. For more information; please refer to Chapter Placeholder. 1: Enabled 0: Disabled, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled, + {EFUSE_BLK0, 48, 3}, // [] Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: Disabled Even count of bits with a value of 1: Enabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled, + {EFUSE_BLK0, 51, 1}, // [] Represents whether PAD JTAG is disabled in the hard way (permanently). 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled, -}; - -static const esp_efuse_desc_t USB_DREFH[] = { - {EFUSE_BLK0, 53, 2}, // [] USB drefh, -}; - -static const esp_efuse_desc_t USB_DREFL[] = { - {EFUSE_BLK0, 55, 2}, // [] USB drefl, + {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encryption is disabled (except in SPI boot mode). 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged, + {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged. 1: Exchanged 0: Not exchanged, }; static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned, + {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: Functioned 0: Not functioned, }; static const esp_efuse_desc_t ECDSA_CURVE_MODE[] = { - {EFUSE_BLK0, 59, 2}, // [] ECDSA curve mode. 0: only P256. 1: only P192. 2: both P192 and P256. 3: only P256, + {EFUSE_BLK0, 59, 2}, // [] Represents the configuration of the curve of ECDSA calculation. 0: Only enable P256 1: Only enable P192 2: Both enable P256 and P192 3: Only enable P256, }; static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { - {EFUSE_BLK0, 61, 1}, // [] ECC force const time, + {EFUSE_BLK0, 61, 1}, // [] Represents whether to permanently turn on ECC const-time mode. 0: Disabled 1: Enabled, }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { - {EFUSE_BLK0, 62, 2}, // [] XTS DPA pseudo level, + {EFUSE_BLK0, 62, 2}, // [] Represents control method of xts pseudo-round anti-dpa attack function. 0: Controlled by register 1-3: The higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation., }; static const esp_efuse_desc_t IO_LDO_ADJUST[] = { @@ -480,11 +420,11 @@ static const esp_efuse_desc_t IO_LDO_ADJUST[] = { }; static const esp_efuse_desc_t VDD_SPI_LDO_ADJUST[] = { - {EFUSE_BLK0, 72, 8}, // [] Represents configuration of FLASH LDO mode and voltage, + {EFUSE_BLK0, 72, 8}, // [] Represents configuration of FLASH LDO mode and voltage., }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected, + {EFUSE_BLK0, 80, 2}, // [] Represents RTC watchdog timeout threshold. 0: The originally configured STG0 threshold x 2 1: The originally configured STG0 threshold x 4 2: The originally configured STG0 threshold x 8 3: The originally configured STG0 threshold x 16, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { @@ -504,75 +444,83 @@ static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { }; static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0, + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0. See Table tab:efuse-key-purpose., }; static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1, + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1. See Table tab:efuse-key-purpose., }; static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2, + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2. See Table tab:efuse-key-purpose., }; static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3, + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3. See Table tab:efuse-key-purpose., }; static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4, + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4. See Table tab:efuse-key-purpose., }; static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5, + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5. See Table tab:efuse-key-purpose., }; static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 112, 2}, // [] Represents the spa secure level by configuring the clock random divide mode, + {EFUSE_BLK0, 112, 2}, // [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode. 0: Security level is SEC_DPA_OFF 1: Security level is SEC_DPA_LOW 2: Security level is SEC_DPA_MIDDLE 3: Security level is SEC_DPA_HIGH For more information; please refer to Chapter mod:sysreg > Section sec:sysreg-anti-dpa-attack-security-control., }; static const esp_efuse_desc_t IO_LDO_1P8[] = { - {EFUSE_BLK0, 114, 1}, // [] Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V, + {EFUSE_BLK0, 114, 1}, // [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V, }; static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = { - {EFUSE_BLK0, 115, 1}, // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled, + {EFUSE_BLK0, 115, 1}, // [] Represents whether defense against DPA attack is enabled. 1: Enabled 0: Disabled, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 116, 1}, // [] Represents whether Secure Boot is enabled. 1: Enabled 0: Disabled, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 117, 1}, // [] Represents whether aggressive revocation of Secure Boot is enabled. 1: Enabled 0: Disabled, }; static const esp_efuse_desc_t POWERGLITCH_EN1[] = { - {EFUSE_BLK0, 118, 5}, // [] Represents whether to enable power glitch function when chip power on, + {EFUSE_BLK0, 118, 5}, // [] Represents whether to enable power glitch function when chip power on., +}; + +static const esp_efuse_desc_t DCDC_CCM_EN[] = { + {EFUSE_BLK0, 123, 1}, // [] Represents whether change DCDC to CCM mode, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, + {EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15; the waiting time is the programmed value. Otherwise; the waiting time is a fixed value; i.e. 30 ms., }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 128, 1}, // [] Represents whether all download modes are disabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot, + {EFUSE_BLK0, 130, 1}, // [] Represents whether print from USB-Serial-JTAG during ROM boot is disabled. 1: Disabled 0: Enabled, +}; + +static const esp_efuse_desc_t FLASH_LDO_EFUSE_SEL[] = { + {EFUSE_BLK0, 131, 1}, // [] Represents whether to select efuse control flash ldo default voltage. 1: efuse0: strapping, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled. Only UART is supported for download. Reading/writing RAM or registers is not supported (i.e. Stub download is not supported). 1: Enabled 0: Disabled, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { @@ -580,23 +528,27 @@ static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced, + {EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: Forced 0: Not forced, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 137, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, + {EFUSE_BLK0, 137, 16}, // [] Represents the security version used by ESP-IDF anti-rollback feature., }; static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. 1: Disabled 0: Enabled, }; static const esp_efuse_desc_t HYS_EN_PAD0[] = { - {EFUSE_BLK0, 154, 6}, // [] Set bits to enable hysteresis function of PAD0~5, + {EFUSE_BLK0, 154, 6}, // [] Represents whether to enable the hysteresis function of pad 0-5. 0: Disabled 1: Enabled, }; static const esp_efuse_desc_t HYS_EN_PAD1[] = { - {EFUSE_BLK0, 160, 22}, // [] Set bits to enable hysteresis function of PAD6~27, + {EFUSE_BLK0, 160, 22}, // [] Represents whether to enable the hysteresis function of pad 6-27. 0: Disabled 1: Enabled, +}; + +static const esp_efuse_desc_t FLASH_LDO_POWER_SEL[] = { + {EFUSE_BLK0, 182, 1}, // [] Represents which flash LDO is selected. 0: FLASH LDO 1P8. 1: FLASH LDO 1P2., }; static const esp_efuse_desc_t MAC[] = { @@ -609,138 +561,77 @@ static const esp_efuse_desc_t MAC[] = { }; static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, - {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, + {EFUSE_BLK1, 48, 16}, // [] Represents the extended bits of MAC address, }; -static const esp_efuse_desc_t RXIQ_VERSION[] = { - {EFUSE_BLK1, 64, 3}, // [] Stores RF Calibration data. RXIQ version, +static const esp_efuse_desc_t PVT_CELL_SELECT[] = { + {EFUSE_BLK1, 100, 7}, // [] Represents the selection of Power glitch monitor PVT cell., }; -static const esp_efuse_desc_t RXIQ_0[] = { - {EFUSE_BLK1, 67, 7}, // [] Stores RF Calibration data. RXIQ data 0, +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 114, 3}, // [] Minor version of BLOCK2, }; -static const esp_efuse_desc_t RXIQ_1[] = { - {EFUSE_BLK1, 74, 7}, // [] Stores RF Calibration data. RXIQ data 1, +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 117, 2}, // [] Major version of BLOCK2, }; -static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { - {EFUSE_BLK1, 81, 5}, // [] Stores the PMU active hp dbias, -}; - -static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { - {EFUSE_BLK1, 86, 5}, // [] Stores the PMU active lp dbias, -}; - -static const esp_efuse_desc_t DSLP_DBIAS[] = { - {EFUSE_BLK1, 91, 4}, // [] Stores the PMU sleep dbias, -}; - -static const esp_efuse_desc_t DBIAS_VOL_GAP[] = { - {EFUSE_BLK1, 95, 5}, // [] Stores the low 1 bit of dbias_vol_gap, -}; - -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 3}, // [] Stores the wafer version minor, -}; - -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 117, 2}, // [] Stores the wafer version major, -}; - -static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 119, 1}, // [] Disables check of wafer version major, +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 119, 1}, // [] Disables check of blk version major, }; static const esp_efuse_desc_t FLASH_CAP[] = { - {EFUSE_BLK1, 120, 3}, // [] Stores the flash cap, -}; - -static const esp_efuse_desc_t FLASH_TEMP[] = { - {EFUSE_BLK1, 123, 2}, // [] Stores the flash temp, + {EFUSE_BLK1, 120, 3}, // [] Mark the capacity of in-package Flash, }; static const esp_efuse_desc_t FLASH_VENDOR[] = { - {EFUSE_BLK1, 125, 3}, // [] Stores the flash vendor, + {EFUSE_BLK1, 123, 3}, // [] Mark the vendor of in-package Flash, +}; + +static const esp_efuse_desc_t TEMP[] = { + {EFUSE_BLK1, 126, 2}, // [] Mark the specified maximum ambient temperature that ESP Chip can work properly, +}; + +static const esp_efuse_desc_t PVT_LIMIT[] = { + {EFUSE_BLK1, 133, 16}, // [] Represents the threshold of power glitch monitor., +}; + +static const esp_efuse_desc_t PVT_GLITCH_CHARGE_RESET[] = { + {EFUSE_BLK1, 149, 1}, // [] Represents whether to trigger reset or charge pump when PVT power glitch happened. 1:Trigger charge pump. 0:Trigger reset, +}; + +static const esp_efuse_desc_t PVT_GLITCH_MODE[] = { + {EFUSE_BLK1, 150, 2}, // [] Represents the configuration of glitch mode., +}; + +static const esp_efuse_desc_t PVT_PUMP_LIMIT[] = { + {EFUSE_BLK1, 152, 8}, // [] Represents the configuration voltage monitor limit for charge pump., +}; + +static const esp_efuse_desc_t PUMP_DRV[] = { + {EFUSE_BLK1, 160, 4}, // [] Use to configure charge pump voltage gain., +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 164, 4}, // [] Minor chip version, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 168, 2}, // [] Major chip version, +}; + +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 170, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 128, 3}, // [] Package version, + {EFUSE_BLK1, 171, 3}, // [] Package version, }; static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; -static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK2, 130, 3}, // [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1, -}; - -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK2, 133, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, -}; - -static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK2, 135, 1}, // [] Disables check of blk version major, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 136, 9}, // [] Temperature calibration data, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK2, 145, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK2, 155, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK2, 165, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK2, 175, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK2, 185, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK2, 195, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK2, 205, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK2, 215, 10}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 225, 4}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 229, 4}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 233, 4}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 237, 4}, // [] ADC1 calibration data, -}; - -static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK2, 241, 4}, // [] ADC1 calibration data, -}; - static const esp_efuse_desc_t USER_DATA[] = { {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, }; @@ -791,6 +682,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[] = { + &WR_DIS_PVT_GLITCH_EN[0], // [] wr_dis of PVT_GLITCH_EN + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE NULL @@ -817,7 +713,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { - &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + &WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI NULL }; @@ -836,6 +732,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN1[] = { + &WR_DIS_POWERGLITCH_EN1[0], // [] wr_dis of POWERGLITCH_EN1 + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL @@ -891,6 +792,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + &WR_DIS_XTS_DPA_PSEUDO_LEVEL[0], // [] wr_dis of XTS_DPA_PSEUDO_LEVEL + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL NULL @@ -937,7 +843,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT NULL }; @@ -996,83 +902,8 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_VERSION[] = { - &WR_DIS_RXIQ_VERSION[0], // [] wr_dis of RXIQ_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_0[] = { - &WR_DIS_RXIQ_0[0], // [] wr_dis of RXIQ_0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[] = { - &WR_DIS_RXIQ_1[0], // [] wr_dis of RXIQ_1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { - &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { - &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBIAS[] = { - &WR_DIS_DSLP_DBIAS[0], // [] wr_dis of DSLP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[] = { - &WR_DIS_DBIAS_VOL_GAP[0], // [] wr_dis of DBIAS_VOL_GAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { - &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { - &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { - &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { - &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { - &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { - &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { - &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_CELL_SELECT[] = { + &WR_DIS_PVT_CELL_SELECT[0], // [] wr_dis of PVT_CELL_SELECT NULL }; @@ -1091,73 +922,73 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { - &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { + &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { + &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = { + &WR_DIS_TEMP[0], // [] wr_dis of TEMP NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_LIMIT[] = { + &WR_DIS_PVT_LIMIT[0], // [] wr_dis of PVT_LIMIT NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[] = { + &WR_DIS_PVT_GLITCH_CHARGE_RESET[0], // [] wr_dis of PVT_GLITCH_CHARGE_RESET NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[] = { + &WR_DIS_PVT_GLITCH_MODE[0], // [] wr_dis of PVT_GLITCH_MODE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_PUMP_LIMIT[] = { + &WR_DIS_PVT_PUMP_LIMIT[0], // [] wr_dis of PVT_PUMP_LIMIT NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PUMP_DRV[] = { + &WR_DIS_PUMP_DRV[0], // [] wr_dis of PUMP_DRV NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; @@ -1262,97 +1093,82 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { }; const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[] = { - &PVT_GLITCH_EN[0], // [] Represents whether pvt glitch is enabled + &PVT_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1: Enable. 0: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // [] Represents whether icache is disabled + &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_JTAG[0], // [] Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { - &POWERGLITCH_EN[0], // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USJ[] = { - &DIS_USJ[0], // [] Represents whether usb serial jtag is disabled + &POWERGLITCH_EN[0], // [] Represents whether to enable power glitch function. NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into Download mode is disabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during boot_mode_download. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { - &DIS_TWAI[0], // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled + &DIS_TWAI[0], // [] Represents whether TWAI function is disabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured to 0. For more information; please refer to Chapter Placeholder. 1: Enabled 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled + &SOFT_DIS_JTAG[0], // [] Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: Disabled Even count of bits with a value of 1: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether PAD JTAG is disabled in the hard way (permanently). 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { - &USB_DREFH[0], // [] USB drefh - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { - &USB_DREFL[0], // [] USB drefl + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encryption is disabled (except in SPI boot mode). 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. 1: Exchanged 0: Not exchanged NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned + &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: Functioned 0: Not functioned NULL }; const esp_efuse_desc_t* ESP_EFUSE_ECDSA_CURVE_MODE[] = { - &ECDSA_CURVE_MODE[0], // [] ECDSA curve mode. 0: only P256. 1: only P192. 2: both P192 and P256. 3: only P256 + &ECDSA_CURVE_MODE[0], // [] Represents the configuration of the curve of ECDSA calculation. 0: Only enable P256 1: Only enable P192 2: Both enable P256 and P192 3: Only enable P256 NULL }; const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { - &ECC_FORCE_CONST_TIME[0], // [] ECC force const time + &ECC_FORCE_CONST_TIME[0], // [] Represents whether to permanently turn on ECC const-time mode. 0: Disabled 1: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { - &XTS_DPA_PSEUDO_LEVEL[0], // [] XTS DPA pseudo level + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents control method of xts pseudo-round anti-dpa attack function. 0: Controlled by register 1-3: The higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation. NULL }; @@ -1362,12 +1178,12 @@ const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_ADJUST[] = { }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[] = { - &VDD_SPI_LDO_ADJUST[0], // [] Represents configuration of FLASH LDO mode and voltage + &VDD_SPI_LDO_ADJUST[0], // [] Represents configuration of FLASH LDO mode and voltage. NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected + &WDT_DELAY_SEL[0], // [] Represents RTC watchdog timeout threshold. 0: The originally configured STG0 threshold x 2 1: The originally configured STG0 threshold x 4 2: The originally configured STG0 threshold x 8 3: The originally configured STG0 threshold x 16 NULL }; @@ -1392,92 +1208,102 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0 + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0. See Table tab:efuse-key-purpose. NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1 + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1. See Table tab:efuse-key-purpose. NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2 + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2. See Table tab:efuse-key-purpose. NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3 + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3. See Table tab:efuse-key-purpose. NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4 + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4. See Table tab:efuse-key-purpose. NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5 + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5. See Table tab:efuse-key-purpose. NULL }; const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { - &SEC_DPA_LEVEL[0], // [] Represents the spa secure level by configuring the clock random divide mode + &SEC_DPA_LEVEL[0], // [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode. 0: Security level is SEC_DPA_OFF 1: Security level is SEC_DPA_LOW 2: Security level is SEC_DPA_MIDDLE 3: Security level is SEC_DPA_HIGH For more information; please refer to Chapter mod:sysreg > Section sec:sysreg-anti-dpa-attack-security-control. NULL }; const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_1P8[] = { - &IO_LDO_1P8[0], // [] Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V + &IO_LDO_1P8[0], // [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V NULL }; const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = { - &CRYPT_DPA_ENABLE[0], // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled + &CRYPT_DPA_ENABLE[0], // [] Represents whether defense against DPA attack is enabled. 1: Enabled 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether Secure Boot is enabled. 1: Enabled 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether aggressive revocation of Secure Boot is enabled. 1: Enabled 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN1[] = { - &POWERGLITCH_EN1[0], // [] Represents whether to enable power glitch function when chip power on + &POWERGLITCH_EN1[0], // [] Represents whether to enable power glitch function when chip power on. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DCDC_CCM_EN[] = { + &DCDC_CCM_EN[0], // [] Represents whether change DCDC to CCM mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value + &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15; the waiting time is the programmed value. Otherwise; the waiting time is a fixed value; i.e. 30 ms. NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DOWNLOAD_MODE[0], // [] Represents whether all download modes are disabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG during ROM boot is disabled. 1: Disabled 0: Enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_EFUSE_SEL[] = { + &FLASH_LDO_EFUSE_SEL[0], // [] Represents whether to select efuse control flash ldo default voltage. 1: efuse0: strapping NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled. Only UART is supported for download. Reading/writing RAM or registers is not supported (i.e. Stub download is not supported). 1: Enabled 0: Disabled NULL }; @@ -1487,27 +1313,32 @@ const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: Forced 0: Not forced NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // [] Represents the version used by ESP-IDF anti-rollback feature + &SECURE_VERSION[0], // [] Represents the security version used by ESP-IDF anti-rollback feature. NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. 1: Disabled 0: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[] = { - &HYS_EN_PAD0[0], // [] Set bits to enable hysteresis function of PAD0~5 + &HYS_EN_PAD0[0], // [] Represents whether to enable the hysteresis function of pad 0-5. 0: Disabled 1: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[] = { - &HYS_EN_PAD1[0], // [] Set bits to enable hysteresis function of PAD6~27 + &HYS_EN_PAD1[0], // [] Represents whether to enable the hysteresis function of pad 6-27. 0: Disabled 1: Enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[] = { + &FLASH_LDO_POWER_SEL[0], // [] Represents which flash LDO is selected. 0: FLASH LDO 1P8. 1: FLASH LDO 1P2. NULL }; @@ -1522,53 +1353,77 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { }; const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // [] Stores the extended bits of MAC address - &MAC_EXT[1], // [] Stores the extended bits of MAC address + &MAC_EXT[0], // [] Represents the extended bits of MAC address NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[] = { - &RXIQ_VERSION[0], // [] Stores RF Calibration data. RXIQ version +const esp_efuse_desc_t* ESP_EFUSE_PVT_CELL_SELECT[] = { + &PVT_CELL_SELECT[0], // [] Represents the selection of Power glitch monitor PVT cell. NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[] = { - &RXIQ_0[0], // [] Stores RF Calibration data. RXIQ data 0 +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // [] Minor version of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[] = { - &RXIQ_1[0], // [] Stores RF Calibration data. RXIQ data 1 +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] Major version of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { - &ACTIVE_HP_DBIAS[0], // [] Stores the PMU active hp dbias +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { - &ACTIVE_LP_DBIAS[0], // [] Stores the PMU active lp dbias +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { + &FLASH_CAP[0], // [] Mark the capacity of in-package Flash NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBIAS[] = { - &DSLP_DBIAS[0], // [] Stores the PMU sleep dbias +const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { + &FLASH_VENDOR[0], // [] Mark the vendor of in-package Flash NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[] = { - &DBIAS_VOL_GAP[0], // [] Stores the low 1 bit of dbias_vol_gap +const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = { + &TEMP[0], // [] Mark the specified maximum ambient temperature that ESP Chip can work properly + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_LIMIT[] = { + &PVT_LIMIT[0], // [] Represents the threshold of power glitch monitor. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[] = { + &PVT_GLITCH_CHARGE_RESET[0], // [] Represents whether to trigger reset or charge pump when PVT power glitch happened. 1:Trigger charge pump. 0:Trigger reset + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[] = { + &PVT_GLITCH_MODE[0], // [] Represents the configuration of glitch mode. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_PUMP_LIMIT[] = { + &PVT_PUMP_LIMIT[0], // [] Represents the configuration voltage monitor limit for charge pump. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PUMP_DRV[] = { + &PUMP_DRV[0], // [] Use to configure charge pump voltage gain. NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // [] Stores the wafer version minor + &WAFER_VERSION_MINOR[0], // [] Minor chip version NULL }; const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // [] Stores the wafer version major + &WAFER_VERSION_MAJOR[0], // [] Major chip version NULL }; @@ -1577,21 +1432,6 @@ const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { - &FLASH_CAP[0], // [] Stores the flash cap - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { - &FLASH_TEMP[0], // [] Stores the flash temp - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { - &FLASH_VENDOR[0], // [] Stores the flash vendor - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { &PKG_VERSION[0], // [] Package version NULL @@ -1602,91 +1442,6 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // [] Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = { - &ADC1_AVE_INITCODE_ATTEN0[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = { - &ADC1_AVE_INITCODE_ATTEN1[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = { - &ADC1_AVE_INITCODE_ATTEN2[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = { - &ADC1_AVE_INITCODE_ATTEN3[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = { - &ADC1_HI_DOUT_ATTEN0[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = { - &ADC1_HI_DOUT_ATTEN1[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = { - &ADC1_HI_DOUT_ATTEN2[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = { - &ADC1_HI_DOUT_ATTEN3[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { &USER_DATA[0], // [BLOCK_USR_DATA] User data NULL diff --git a/components/efuse/esp32h21/esp_efuse_table.csv b/components/efuse/esp32h21/esp_efuse_table.csv index 7cc4ae4b24e..a5e80ed0a16 100644 --- a/components/efuse/esp32h21/esp_efuse_table.csv +++ b/components/efuse/esp32h21/esp_efuse_table.csv @@ -9,21 +9,21 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# TODO: [ESP32H21] IDF-11556, file inherit from verify code, please check - -# This file was generated by regtools.py based on the efuses.yaml file with the version: ef562916e77cf77203c1a4c0cff35ac5 +# This file was generated by regtools.py based on the efuses.yaml file with the version: fdae7598a57fba48c608b1747e3d3d65 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.PVT_GLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_EN WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG WR_DIS.POWERGLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of POWERGLITCH_EN WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.POWERGLITCH_EN1, EFUSE_BLK0, 2, 1, [] wr_dis of POWERGLITCH_EN1 WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 @@ -35,6 +35,7 @@ WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.K WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN @@ -44,7 +45,7 @@ WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 17, 1, [] wr_dis WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL @@ -56,39 +57,24 @@ WR_DIS.HYS_EN_PAD1, EFUSE_BLK0, 19, 1, [] wr_dis WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.RXIQ_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_VERSION -WR_DIS.RXIQ_0, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_0 -WR_DIS.RXIQ_1, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_1 -WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS -WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS -WR_DIS.DSLP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBIAS -WR_DIS.DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of DBIAS_VOL_GAP +WR_DIS.PVT_CELL_SELECT, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_CELL_SELECT +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP +WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR +WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP +WR_DIS.PVT_LIMIT, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_LIMIT +WR_DIS.PVT_GLITCH_CHARGE_RESET, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_GLITCH_CHARGE_RESET +WR_DIS.PVT_GLITCH_MODE, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_GLITCH_MODE +WR_DIS.PVT_PUMP_LIMIT, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_PUMP_LIMIT +WR_DIS.PUMP_DRV, EFUSE_BLK0, 20, 1, [] wr_dis of PUMP_DRV WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP -WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP -WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 -WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 -WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 -WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 -WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0 -WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1 -WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2 -WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3 -WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -109,96 +95,80 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -PVT_GLITCH_EN, EFUSE_BLK0, 39, 1, [] Represents whether pvt glitch is enabled -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled -DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -POWERGLITCH_EN, EFUSE_BLK0, 42, 1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled -DIS_USJ, EFUSE_BLK0, 43, 1, [] Represents whether usb serial jtag is disabled -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -USB_DREFH, EFUSE_BLK0, 53, 2, [] USB drefh -USB_DREFL, EFUSE_BLK0, 55, 2, [] USB drefl -USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged -VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned -ECDSA_CURVE_MODE, EFUSE_BLK0, 59, 2, [] ECDSA curve mode. 0: only P256. 1: only P192. 2: both P192 and P256. 3: only P256 -ECC_FORCE_CONST_TIME, EFUSE_BLK0, 61, 1, [] ECC force const time -XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 62, 2, [] XTS DPA pseudo level +PVT_GLITCH_EN, EFUSE_BLK0, 39, 1, [] Represents whether to enable PVT power glitch monitor function.1: Enable. 0: Disable +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled. 1: Disabled 0: Enabled +DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. 1: Disabled 0: Enabled +POWERGLITCH_EN, EFUSE_BLK0, 42, 1, [] Represents whether to enable power glitch function. +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into Download mode is disabled. 1: Disabled 0: Enabled +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during boot_mode_download. 1: Disabled 0: Enabled +DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled. 1: Disabled 0: Enabled +JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection of a JTAG signal source through the strapping pin value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured to 0. For more information; please refer to Chapter Placeholder. 1: Enabled 0: Disabled +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether PAD JTAG is disabled in the soft way. It can be restarted via HMAC. Odd count of bits with a value of 1: Disabled Even count of bits with a value of 1: Enabled +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether PAD JTAG is disabled in the hard way (permanently). 1: Disabled 0: Enabled +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encryption is disabled (except in SPI boot mode). 1: Disabled 0: Enabled +USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: Exchanged 0: Not exchanged +VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: Functioned 0: Not functioned +ECDSA_CURVE_MODE, EFUSE_BLK0, 59, 2, [] Represents the configuration of the curve of ECDSA calculation. 0: Only enable P256 1: Only enable P192 2: Both enable P256 and P192 3: Only enable P256 +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 61, 1, [] Represents whether to permanently turn on ECC const-time mode. 0: Disabled 1: Enabled +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 62, 2, [] Represents control method of xts pseudo-round anti-dpa attack function. 0: Controlled by register 1-3: The higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation. IO_LDO_ADJUST, EFUSE_BLK0, 64, 8, [] Represents configuration of IO LDO mode and voltage. -VDD_SPI_LDO_ADJUST, EFUSE_BLK0, 72, 8, [] Represents configuration of FLASH LDO mode and voltage -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected +VDD_SPI_LDO_ADJUST, EFUSE_BLK0, 72, 8, [] Represents configuration of FLASH LDO mode and voltage. +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents RTC watchdog timeout threshold. 0: The originally configured STG0 threshold x 2 1: The originally configured STG0 threshold x 4 2: The originally configured STG0 threshold x 8 3: The originally configured STG0 threshold x 16 SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5 -SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode -IO_LDO_1P8, EFUSE_BLK0, 114, 1, [] Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V -CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled -POWERGLITCH_EN1, EFUSE_BLK0, 118, 5, [] Represents whether to enable power glitch function when chip power on -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0. See Table tab:efuse-key-purpose. +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1. See Table tab:efuse-key-purpose. +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2. See Table tab:efuse-key-purpose. +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3. See Table tab:efuse-key-purpose. +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4. See Table tab:efuse-key-purpose. +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5. See Table tab:efuse-key-purpose. +SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode. 0: Security level is SEC_DPA_OFF 1: Security level is SEC_DPA_LOW 2: Security level is SEC_DPA_MIDDLE 3: Security level is SEC_DPA_HIGH For more information; please refer to Chapter mod:sysreg > Section sec:sysreg-anti-dpa-attack-security-control. +IO_LDO_1P8, EFUSE_BLK0, 114, 1, [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V +CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, [] Represents whether defense against DPA attack is enabled. 1: Enabled 0: Disabled +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether Secure Boot is enabled. 1: Enabled 0: Disabled +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether aggressive revocation of Secure Boot is enabled. 1: Enabled 0: Disabled +POWERGLITCH_EN1, EFUSE_BLK0, 118, 5, [] Represents whether to enable power glitch function when chip power on. +DCDC_CCM_EN, EFUSE_BLK0, 123, 1, [] Represents whether change DCDC to CCM mode +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up. Measurement unit: ms. When the value is less than 15; the waiting time is the programmed value. Otherwise; the waiting time is a fixed value; i.e. 30 ms. +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether all download modes are disabled. 1: Disabled 0: Enabled +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled. 1: Disabled 0: Enabled +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Represents whether print from USB-Serial-JTAG during ROM boot is disabled. 1: Disabled 0: Enabled +FLASH_LDO_EFUSE_SEL, EFUSE_BLK0, 131, 1, [] Represents whether to select efuse control flash ldo default voltage. 1: efuse0: strapping +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled. 1: Disabled 0: Enabled +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled. Only UART is supported for download. Reading/writing RAM or registers is not supported (i.e. Stub download is not supported). 1: Enabled 0: Disabled UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced -SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -HYS_EN_PAD0, EFUSE_BLK0, 154, 6, [] Set bits to enable hysteresis function of PAD0~5 -HYS_EN_PAD1, EFUSE_BLK0, 160, 22, [] Set bits to enable hysteresis function of PAD6~27 +FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: Forced 0: Not forced +SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the security version used by ESP-IDF anti-rollback feature. +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. 1: Disabled 0: Enabled +HYS_EN_PAD0, EFUSE_BLK0, 154, 6, [] Represents whether to enable the hysteresis function of pad 0-5. 0: Disabled 1: Enabled +HYS_EN_PAD1, EFUSE_BLK0, 160, 22, [] Represents whether to enable the hysteresis function of pad 6-27. 0: Disabled 1: Enabled +FLASH_LDO_POWER_SEL, EFUSE_BLK0, 182, 1, [] Represents which flash LDO is selected. 0: FLASH LDO 1P8. 1: FLASH LDO 1P2. MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address -, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address -RXIQ_VERSION, EFUSE_BLK1, 64, 3, [] Stores RF Calibration data. RXIQ version -RXIQ_0, EFUSE_BLK1, 67, 7, [] Stores RF Calibration data. RXIQ data 0 -RXIQ_1, EFUSE_BLK1, 74, 7, [] Stores RF Calibration data. RXIQ data 1 -ACTIVE_HP_DBIAS, EFUSE_BLK1, 81, 5, [] Stores the PMU active hp dbias -ACTIVE_LP_DBIAS, EFUSE_BLK1, 86, 5, [] Stores the PMU active lp dbias -DSLP_DBIAS, EFUSE_BLK1, 91, 4, [] Stores the PMU sleep dbias -DBIAS_VOL_GAP, EFUSE_BLK1, 95, 5, [] Stores the low 1 bit of dbias_vol_gap -WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, [] Stores the wafer version minor -WAFER_VERSION_MAJOR, EFUSE_BLK1, 117, 2, [] Stores the wafer version major -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 119, 1, [] Disables check of wafer version major -FLASH_CAP, EFUSE_BLK1, 120, 3, [] Stores the flash cap -FLASH_TEMP, EFUSE_BLK1, 123, 2, [] Stores the flash temp -FLASH_VENDOR, EFUSE_BLK1, 125, 3, [] Stores the flash vendor -PKG_VERSION, EFUSE_BLK1, 128, 3, [] Package version +MAC_EXT, EFUSE_BLK1, 48, 16, [] Represents the extended bits of MAC address +PVT_CELL_SELECT, EFUSE_BLK1, 100, 7, [] Represents the selection of Power glitch monitor PVT cell. +BLK_VERSION_MINOR, EFUSE_BLK1, 114, 3, [] Minor version of BLOCK2 +BLK_VERSION_MAJOR, EFUSE_BLK1, 117, 2, [] Major version of BLOCK2 +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 119, 1, [] Disables check of blk version major +FLASH_CAP, EFUSE_BLK1, 120, 3, [] Mark the capacity of in-package Flash +FLASH_VENDOR, EFUSE_BLK1, 123, 3, [] Mark the vendor of in-package Flash +TEMP, EFUSE_BLK1, 126, 2, [] Mark the specified maximum ambient temperature that ESP Chip can work properly +PVT_LIMIT, EFUSE_BLK1, 133, 16, [] Represents the threshold of power glitch monitor. +PVT_GLITCH_CHARGE_RESET, EFUSE_BLK1, 149, 1, [] Represents whether to trigger reset or charge pump when PVT power glitch happened. 1:Trigger charge pump. 0:Trigger reset +PVT_GLITCH_MODE, EFUSE_BLK1, 150, 2, [] Represents the configuration of glitch mode. +PVT_PUMP_LIMIT, EFUSE_BLK1, 152, 8, [] Represents the configuration voltage monitor limit for charge pump. +PUMP_DRV, EFUSE_BLK1, 160, 4, [] Use to configure charge pump voltage gain. +WAFER_VERSION_MINOR, EFUSE_BLK1, 164, 4, [] Minor chip version +WAFER_VERSION_MAJOR, EFUSE_BLK1, 168, 2, [] Major chip version +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 170, 1, [] Disables check of wafer version major +PKG_VERSION, EFUSE_BLK1, 171, 3, [] Package version OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -BLK_VERSION_MINOR, EFUSE_BLK2, 130, 3, [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 -BLK_VERSION_MAJOR, EFUSE_BLK2, 133, 2, [] BLK_VERSION_MAJOR of BLOCK2 -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK2, 135, 1, [] Disables check of blk version major -TEMP_CALIB, EFUSE_BLK2, 136, 9, [] Temperature calibration data -ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 calibration data -ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 calibration data -ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 calibration data -ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 calibration data -ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration data -ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration data -ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration data -ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration data -ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] ADC1 calibration data -ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] ADC1 calibration data -ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] ADC1 calibration data -ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] ADC1 calibration data -ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 241, 4, [] ADC1 calibration data USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data diff --git a/components/efuse/esp32h21/include/esp_efuse_chip.h b/components/efuse/esp32h21/include/esp_efuse_chip.h index 3845112c034..ce8b4da9745 100644 --- a/components/efuse/esp32h21/include/esp_efuse_chip.h +++ b/components/efuse/esp32h21/include/esp_efuse_chip.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: [ESP32H21] IDF-11556, file inherit from verify code, please check - /** * @brief Type of eFuse blocks ESP32H21 */ diff --git a/components/efuse/esp32h21/include/esp_efuse_table.h b/components/efuse/esp32h21/include/esp_efuse_table.h index fcbaf9acf3f..3eb62646f55 100644 --- a/components/efuse/esp32h21/include/esp_efuse_table.h +++ b/components/efuse/esp32h21/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 4ec5511e3b738f65373b56d5cdecea93 +// md5_digest_table d2954679788e8cfb56ac5273aa5ed838 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,16 +19,17 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; -#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; @@ -46,6 +47,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; #define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; #define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; @@ -56,7 +58,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; @@ -69,39 +70,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_CELL_SELECT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_PUMP_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PUMP_DRV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -143,17 +129,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USJ[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; -#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_CURVE_MODE[]; @@ -184,11 +166,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_CCM_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_EFUSE_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; @@ -197,41 +180,27 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[]; extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_CELL_SELECT[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_PUMP_LIMIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PUMP_DRV[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; diff --git a/components/esp_hal_security/esp32h21/include/hal/ecdsa_ll.h b/components/esp_hal_security/esp32h21/include/hal/ecdsa_ll.h index 9aedb455d2d..df7b9cb690d 100644 --- a/components/esp_hal_security/esp32h21/include/hal/ecdsa_ll.h +++ b/components/esp_hal_security/esp32h21/include/hal/ecdsa_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -424,8 +424,27 @@ static inline bool ecdsa_ll_is_deterministic_mode_supported(void) */ __attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { - (void) curve; - (void) efuse_blk; + uint8_t efuse_blk_low = 0; + uint8_t efuse_blk_high = 0; + + switch (curve) { + case ECDSA_CURVE_SECP192R1: + EFUSE.conf.cfg_ecdsa_l_blk = efuse_blk; + break; + case ECDSA_CURVE_SECP256R1: + EFUSE.conf.cfg_ecdsa_l_blk = efuse_blk; + break; + case ECDSA_CURVE_SECP384R1: + // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer + // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number. + HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low); + EFUSE.conf.cfg_ecdsa_h_blk = efuse_blk_high; + EFUSE.conf.cfg_ecdsa_l_blk = efuse_blk_low; + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + break; + } } /** diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h b/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h index a4429c44032..3ec959eb7cb 100644 --- a/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h @@ -14,8 +14,6 @@ extern "C" { #include #include -//TODO: [ESP32H21] IDF-11556 - /** \defgroup efuse_APIs efuse APIs * @brief ESP32H21 efuse read/write APIs * @attention diff --git a/components/hal/esp32h21/efuse_hal.c b/components/hal/esp32h21/efuse_hal.c index 8f7b83ca48c..d60226f1e30 100644 --- a/components/hal/esp32h21/efuse_hal.c +++ b/components/hal/esp32h21/efuse_hal.c @@ -11,8 +11,6 @@ #include "hal/efuse_ll.h" #include "esp_attr.h" -//TODO: [ESP32H21] IDF-11556 - #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block)))) #define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block)))) diff --git a/components/hal/esp32h21/include/hal/efuse_hal.h b/components/hal/esp32h21/include/hal/efuse_hal.h index 92f3d3eb70a..9a442ac47cc 100644 --- a/components/hal/esp32h21/include/hal/efuse_hal.h +++ b/components/hal/esp32h21/include/hal/efuse_hal.h @@ -12,8 +12,6 @@ #include "hal/efuse_ll.h" #include_next "hal/efuse_hal.h" -//TODO: [ESP32H21] IDF-11556, inherit from h2 - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32h21/include/hal/efuse_ll.h b/components/hal/esp32h21/include/hal/efuse_ll.h index d26fb9b9393..5457ef61ce3 100644 --- a/components/hal/esp32h21/include/hal/efuse_ll.h +++ b/components/hal/esp32h21/include/hal/efuse_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,8 +13,6 @@ #include "hal/assert.h" #include "rom/efuse.h" -//TODO: [ESP32H21] IDF-11556, inherit from h2 - #ifdef __cplusplus extern "C" { #endif @@ -40,12 +38,12 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_sys_0.mac_0; + return EFUSE.rd_mac_sys0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_mac_sys_1.mac_1; + return EFUSE.rd_mac_sys1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) @@ -56,51 +54,48 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys5.wafer_version_major; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys5.wafer_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys5.disable_wafer_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys3.blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys3.blk_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys3.disable_blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.rd_mac_sys5.pkg_version; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void) { - //TODO: [ESP32H21] IDF-11556 - return 0; + return EFUSE.status.cur_ecdsa_l_blk; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_hi_blk(void) +{ + return EFUSE.status.cur_ecdsa_h_blk; } /******************* eFuse control functions *************************/ diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 752718de154..83b0ad9e50a 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -40,7 +40,7 @@ // #define SOC_SUPPORTS_SECURE_DL_MODE 1 // #define SOC_ULP_SUPPORTED 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 -#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11556 +#define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548 #define SOC_I2S_SUPPORTED 1 diff --git a/components/soc/esp32h21/register/soc/efuse_reg.h b/components/soc/esp32h21/register/soc/efuse_reg.h index 40ff63984dd..66a9c1e75b4 100644 --- a/components/soc/esp32h21/register/soc/efuse_reg.h +++ b/components/soc/esp32h21/register/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -149,9 +149,7 @@ extern "C" { #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled.\\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -164,52 +162,52 @@ extern "C" { #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled.\\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 /** EFUSE_PVT_GLITCH_EN : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1: Enable. - * 0: Disable + * Represents whether to enable PVT power glitch monitor function.\\1: Enable. \\0: + * Disable\\ */ #define EFUSE_PVT_GLITCH_EN (BIT(7)) #define EFUSE_PVT_GLITCH_EN_M (EFUSE_PVT_GLITCH_EN_V << EFUSE_PVT_GLITCH_EN_S) #define EFUSE_PVT_GLITCH_EN_V 0x00000001U #define EFUSE_PVT_GLITCH_EN_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. - * 1: Disabled - * 0: Enabled + * Represents whether icache is disabled or enabled.\\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) #define EFUSE_DIS_ICACHE_V 0x00000001U #define EFUSE_DIS_ICACHE_S 8 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. \\ 1: + * Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_USB_JTAG (BIT(9)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 /** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether to enable power glitch function. + * Represents whether to enable power glitch function.\\ */ #define EFUSE_POWERGLITCH_EN (BIT(10)) #define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) #define EFUSE_POWERGLITCH_EN_V 0x00000001U #define EFUSE_POWERGLITCH_EN_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether to disable USB-Serial-JTAG.\\ + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function that forces chip into Download mode is disabled. \\ + * 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) @@ -217,18 +215,14 @@ extern "C" { #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during - * boot_mode_download. - * 1: Disabled - * 0: Enabled + * boot_mode_download.\\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether TWAI function is disabled. \\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) @@ -237,9 +231,8 @@ extern "C" { /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; * Represents whether the selection of a JTAG signal source through the strapping pin * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured - * to 0. For more information, please refer to Chapter Placeholder. - * 1: Enabled - * 0: Disabled + * to 0. For more information, please refer to Chapter Placeholder.\\ 1: Enabled\\ 0: + * Disabled\\ */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) @@ -247,75 +240,81 @@ extern "C" { #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled + * HMAC. \\ Odd count of bits with a value of 1: Disabled\\ Even count of bits with a + * value of 1: Enabled\\ */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled + * Represents whether PAD JTAG is disabled in the hard way (permanently).\\ 1: + * Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) #define EFUSE_DIS_PAD_JTAG_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled + * Represents whether flash encryption is disabled (except in SPI boot mode).\\ 1: + * Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, + * stored in eFuse.\\ + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse.\\ + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged + * Represents whether the D+ and D- pins is exchanged.\\ 1: Exchanged\\ 0: Not + * exchanged\\ */ #define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) #define EFUSE_USB_EXCHG_PINS_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_S 25 /** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. - * 1: Functioned - * 0: Not functioned + * Represents whether vdd spi pin is functioned as gpio.\\ 1: Functioned\\ 0: Not + * functioned\\ */ #define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 26 /** EFUSE_ECDSA_CURVE_MODE : RO; bitpos: [28:27]; default: 0; - * Represents the configuration of the curve of ECDSA calculation. - * 0: Only enable P256 - * 1: Only enable P192 - * 2: Both enable P256 and P192 - * 3: Only enable P256 + * Represents the configuration of the curve of ECDSA calculation.\\ 0: Only enable + * P256\\ 1: Only enable P192\\ 2: Both enable P256 and P192\\ 3: Only enable P256\\ */ #define EFUSE_ECDSA_CURVE_MODE 0x00000003U #define EFUSE_ECDSA_CURVE_MODE_M (EFUSE_ECDSA_CURVE_MODE_V << EFUSE_ECDSA_CURVE_MODE_S) #define EFUSE_ECDSA_CURVE_MODE_V 0x00000003U #define EFUSE_ECDSA_CURVE_MODE_S 27 /** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [29]; default: 0; - * Represents whether to permanently turn on ECC const-time mode. - * 0: Disabled - * 1: Enabled + * Represents whether to permanently turn on ECC const-time mode.\\ 0: Disabled\\ 1: + * Enabled\\ */ #define EFUSE_ECC_FORCE_CONST_TIME (BIT(29)) #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_S 29 /** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [31:30]; default: 0; - * Represents control method of xts pseudo-round anti-dpa attack function. - * 0: Controlled by register - * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation. + * Represents control method of xts pseudo-round anti-dpa attack function.\\ 0: + * Controlled by register\\ 1-3: The higher the value is, the more pseudo-rounds are + * inserted to the xts-aes calculation.\\ */ #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) @@ -327,75 +326,69 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) /** EFUSE_IO_LDO_ADJUST : RO; bitpos: [7:0]; default: 0; - * Represents configuration of IO LDO mode and voltage. + * Represents configuration of IO LDO mode and voltage.\\ */ #define EFUSE_IO_LDO_ADJUST 0x000000FFU #define EFUSE_IO_LDO_ADJUST_M (EFUSE_IO_LDO_ADJUST_V << EFUSE_IO_LDO_ADJUST_S) #define EFUSE_IO_LDO_ADJUST_V 0x000000FFU #define EFUSE_IO_LDO_ADJUST_S 0 /** EFUSE_VDD_SPI_LDO_ADJUST : RO; bitpos: [15:8]; default: 0; - * Represents configuration of FLASH LDO mode and voltage. + * Represents configuration of FLASH LDO mode and voltage.\\ */ #define EFUSE_VDD_SPI_LDO_ADJUST 0x000000FFU #define EFUSE_VDD_SPI_LDO_ADJUST_M (EFUSE_VDD_SPI_LDO_ADJUST_V << EFUSE_VDD_SPI_LDO_ADJUST_S) #define EFUSE_VDD_SPI_LDO_ADJUST_V 0x000000FFU #define EFUSE_VDD_SPI_LDO_ADJUST_S 8 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0：The originally configured STG0 threshold × 2 - * 1：The originally configured STG0 threshold × 4 - * 2：The originally configured STG0 threshold × 8 - * 3：The originally configured STG0 threshold × 16 + * Represents RTC watchdog timeout threshold. 0: The originally configured STG0 + * threshold x 2 1: The originally configured STG0 threshold x 4 2: The originally + * configured STG0 threshold x 8 3: The originally configured STG0 threshold x 16 */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) #define EFUSE_WDT_DELAY_SEL_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled + * Represents whether SPI boot encryption/decryption is enabled. \\ Odd count of bits + * with a value of 1: Enabled\\ Even count of bits with a value of 1: Disabled\\ */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key 0 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking Secure Boot key 0 is enabled. \\ 1: Enabled\\ 0: + * Disabled\\ */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking Secure Boot key 1 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking Secure Boot key 1 is enabled. \\ 1: Enabled\\ 0: + * Disabled\\ */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking Secure Boot key 2 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking Secure Boot key 2 is enabled. \\ 1: Enabled\\ 0: + * Disabled\\ */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. See Table tab:efuse-key-purpose. + * Represents the purpose of Key0. See Table tab:efuse-key-purpose.\\ */ #define EFUSE_KEY_PURPOSE_0 0x0000000FU #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_S 24 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. See Table tab:efuse-key-purpose. + * Represents the purpose of Key1. See Table tab:efuse-key-purpose.\\ */ #define EFUSE_KEY_PURPOSE_1 0x0000000FU #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) @@ -407,28 +400,28 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. See Table tab:efuse-key-purpose. + * Represents the purpose of Key2. See Table tab:efuse-key-purpose.\\ */ #define EFUSE_KEY_PURPOSE_2 0x0000000FU #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. See Table tab:efuse-key-purpose. + * Represents the purpose of Key3. See Table tab:efuse-key-purpose.\\ */ #define EFUSE_KEY_PURPOSE_3 0x0000000FU #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_S 4 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. See Table tab:efuse-key-purpose. + * Represents the purpose of Key4. See Table tab:efuse-key-purpose.\\ */ #define EFUSE_KEY_PURPOSE_4 0x0000000FU #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_S 8 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. See Table tab:efuse-key-purpose. + * Represents the purpose of Key5. See Table tab:efuse-key-purpose.\\ */ #define EFUSE_KEY_PURPOSE_5 0x0000000FU #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) @@ -436,56 +429,47 @@ extern "C" { #define EFUSE_KEY_PURPOSE_5_S 12 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC_DPA_OFF - * 1: Security level is SEC_DPA_LOW - * 2: Security level is SEC_DPA_MIDDLE - * 3: Security level is SEC_DPA_HIGH - * For more information, please refer to Chapter mod:sysreg > Section - * sec:sysreg-anti-dpa-attack-security-control. + * configuring the clock random frequency division mode.\\ 0: Security level is + * SEC_DPA_OFF\\ 1: Security level is SEC_DPA_LOW\\ 2: Security level is + * SEC_DPA_MIDDLE\\ 3: Security level is SEC_DPA_HIGH\\ For more information, please + * refer to Chapter mod:sysreg > Section sec:sysreg-anti-dpa-attack-security-control.\\ */ #define EFUSE_SEC_DPA_LEVEL 0x00000003U #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 /** EFUSE_IO_LDO_1P8 : RO; bitpos: [18]; default: 0; - * Represents select IO LDO voltage to 1.8V or 3.3V. - * 1: 1.8V - * 0: 3.3V + * Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V\\ */ #define EFUSE_IO_LDO_1P8 (BIT(18)) #define EFUSE_IO_LDO_1P8_M (EFUSE_IO_LDO_1P8_V << EFUSE_IO_LDO_1P8_S) #define EFUSE_IO_LDO_1P8_V 0x00000001U #define EFUSE_IO_LDO_1P8_S 18 /** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 0; - * Represents whether defense against DPA attack is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether defense against DPA attack is enabled.\\ 1: Enabled\\ 0: + * Disabled\\ */ #define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) #define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_S 19 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether Secure Boot is enabled.\\ 1: Enabled\\ 0: Disabled\\ */ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether aggressive revocation of Secure Boot is enabled.\\ 1: Enabled\\ + * 0: Disabled\\ */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 /** EFUSE_POWERGLITCH_EN1 : RO; bitpos: [26:22]; default: 0; - * Represents whether to enable power glitch function when chip power on. + * Represents whether to enable power glitch function when chip power on.\\ */ #define EFUSE_POWERGLITCH_EN1 0x0000001FU #define EFUSE_POWERGLITCH_EN1_M (EFUSE_POWERGLITCH_EN1_V << EFUSE_POWERGLITCH_EN1_S) @@ -499,9 +483,9 @@ extern "C" { #define EFUSE_DCDC_CCM_EN_V 0x00000001U #define EFUSE_DCDC_CCM_EN_S 27 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. - * When the value is less than 15, the waiting time is the programmed value. - * Otherwise, the waiting time is a fixed value, i.e. 30 ms. + * Represents the flash waiting time after power-up. Measurement unit: ms.\\ When the + * value is less than 15, the waiting time is the programmed value. Otherwise, the + * waiting time is a fixed value, i.e. 30 ms.\\ */ #define EFUSE_FLASH_TPUW 0x0000000FU #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) @@ -513,45 +497,38 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether all download modes are disabled. - * 1: Disabled - * 0: Enabled + * Represents whether all download modes are disabled.\\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether direct boot mode is disabled.\\ 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether print from USB-Serial-JTAG during ROM boot is disabled.\\ 1: + * Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 /** EFUSE_FLASH_LDO_EFUSE_SEL : RO; bitpos: [3]; default: 0; - * Represents whether to select efuse control flash ldo default voltage. - * 1: efuse - * 0: strapping + * Represents whether to select efuse control flash ldo default voltage. \\1: + * efuse\\0: strapping\\ */ #define EFUSE_FLASH_LDO_EFUSE_SEL (BIT(3)) #define EFUSE_FLASH_LDO_EFUSE_SEL_M (EFUSE_FLASH_LDO_EFUSE_SEL_V << EFUSE_FLASH_LDO_EFUSE_SEL_S) #define EFUSE_FLASH_LDO_EFUSE_SEL_V 0x00000001U #define EFUSE_FLASH_LDO_EFUSE_SEL_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-Serial-JTAG download function is disabled.\\ 1: + * Disabled\\ 0: Enabled\\ */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) @@ -560,54 +537,47 @@ extern "C" { /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; * Represents whether security download is enabled. Only UART is supported for * download. Reading/writing RAM or registers is not supported (i.e. Stub download is - * not supported). - * 1: Enabled - * 0: Disabled + * not supported).\\ 1: Enabled\\ 0: Disabled\\ */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO8 is reset at low level. - * 2: Enable printing when GPIO8 is reset at high level. - * 3: Force disable printing. + * Represents the type of UART printing.\\ 0: Force enable printing.\\ 1: Enable + * printing when GPIO8 is reset at low level.\\ 2: Enable printing when GPIO8 is reset + * at high level.\\ 3: Force disable printing.\\ */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced - * 0: Not forced + * Represents whether ROM code is forced to send a resume command during SPI boot.\\ + * 1: Forced\\ 0: Not forced\\ */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 8 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the security version used by ESP-IDF anti-rollback feature. + * Represents the security version used by ESP-IDF anti-rollback feature.\\ */ #define EFUSE_SECURE_VERSION 0x0000FFFFU #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) #define EFUSE_SECURE_VERSION_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.\\ + * 1: Disabled\\ 0: Enabled\\ */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 /** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0; - * Represents whether to enable the hysteresis function of pad 0-5. - * 0: Disabled - * 1: Enabled + * Represents whether to enable the hysteresis function of pad 0-5.\\ 0: Disabled\\ 1: + * Enabled\\ */ #define EFUSE_HYS_EN_PAD0 0x0000003FU #define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S) @@ -619,18 +589,15 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) /** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0; - * Represents whether to enable the hysteresis function of pad 6-27. - * 0: Disabled - * 1: Enabled + * Represents whether to enable the hysteresis function of pad 6-27.\\ 0: Disabled\\ + * 1: Enabled\\ */ #define EFUSE_HYS_EN_PAD1 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S) #define EFUSE_HYS_EN_PAD1_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_S 0 /** EFUSE_FLASH_LDO_POWER_SEL : RO; bitpos: [22]; default: 0; - * Represents which flash LDO is selected. - * 0: FLASH LDO 1P8. - * 1: FLASH LDO 1P2. + * Represents which flash LDO is selected.\\ 0: FLASH LDO 1P8.\\ 1: FLASH LDO 1P2.\\ */ #define EFUSE_FLASH_LDO_POWER_SEL (BIT(22)) #define EFUSE_FLASH_LDO_POWER_SEL_M (EFUSE_FLASH_LDO_POWER_SEL_V << EFUSE_FLASH_LDO_POWER_SEL_S) @@ -699,7 +666,7 @@ extern "C" { #define EFUSE_MAC_RESERVED_2_V 0x0000000FU #define EFUSE_MAC_RESERVED_2_S 0 /** EFUSE_PVT_CELL_SELECT : RO; bitpos: [10:4]; default: 0; - * Represents the selection of Power glitch monitor PVT cell. + * Represents the selection of Power glitch monitor PVT cell.\\ */ #define EFUSE_PVT_CELL_SELECT 0x0000007FU #define EFUSE_PVT_CELL_SELECT_M (EFUSE_PVT_CELL_SELECT_V << EFUSE_PVT_CELL_SELECT_S) @@ -712,43 +679,77 @@ extern "C" { #define EFUSE_MAC_RESERVED_3_M (EFUSE_MAC_RESERVED_3_V << EFUSE_MAC_RESERVED_3_S) #define EFUSE_MAC_RESERVED_3_V 0x0000007FU #define EFUSE_MAC_RESERVED_3_S 11 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [20:18]; default: 0; + * Minor version of BLOCK2 */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 18 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [22:21]; default: 0; + * Major version of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 21 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [23]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(23)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 23 +/** EFUSE_FLASH_CAP : R; bitpos: [26:24]; default: 0; + * Mark the capacity of in-package Flash + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 24 +/** EFUSE_FLASH_VENDOR : R; bitpos: [29:27]; default: 0; + * Mark the vendor of in-package Flash + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 27 +/** EFUSE_TEMP : R; bitpos: [31:30]; default: 0; + * Mark the specified maximum ambient temperature that ESP Chip can work properly + */ +#define EFUSE_TEMP 0x00000003U +#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S) +#define EFUSE_TEMP_V 0x00000003U +#define EFUSE_TEMP_S 30 /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) /** EFUSE_PVT_LIMIT : RO; bitpos: [20:5]; default: 0; - * Represents the threshold of power glitch monitor. + * Represents the threshold of power glitch monitor.\\ */ #define EFUSE_PVT_LIMIT 0x0000FFFFU #define EFUSE_PVT_LIMIT_M (EFUSE_PVT_LIMIT_V << EFUSE_PVT_LIMIT_S) #define EFUSE_PVT_LIMIT_V 0x0000FFFFU #define EFUSE_PVT_LIMIT_S 5 /** EFUSE_PVT_GLITCH_CHARGE_RESET : RO; bitpos: [21]; default: 0; - * Represents whether to trigger reset or charge pump when PVT power glitch happened. - * 1:Trigger charge pump. - * 0:Trigger reset + * Represents whether to trigger reset or charge pump when PVT power glitch + * happened.\\ 1:Trigger charge pump. \\ 0:Trigger reset\\ */ #define EFUSE_PVT_GLITCH_CHARGE_RESET (BIT(21)) #define EFUSE_PVT_GLITCH_CHARGE_RESET_M (EFUSE_PVT_GLITCH_CHARGE_RESET_V << EFUSE_PVT_GLITCH_CHARGE_RESET_S) #define EFUSE_PVT_GLITCH_CHARGE_RESET_V 0x00000001U #define EFUSE_PVT_GLITCH_CHARGE_RESET_S 21 /** EFUSE_PVT_GLITCH_MODE : RO; bitpos: [23:22]; default: 0; - * Represents the configuration of glitch mode. + * Represents the configuration of glitch mode.\\ */ #define EFUSE_PVT_GLITCH_MODE 0x00000003U #define EFUSE_PVT_GLITCH_MODE_M (EFUSE_PVT_GLITCH_MODE_V << EFUSE_PVT_GLITCH_MODE_S) #define EFUSE_PVT_GLITCH_MODE_V 0x00000003U #define EFUSE_PVT_GLITCH_MODE_S 22 /** EFUSE_PVT_PUMP_LIMIT : RO; bitpos: [31:24]; default: 0; - * Represents the configuration voltage monitor limit for charge pump. + * Represents the configuration voltage monitor limit for charge pump.\\ */ #define EFUSE_PVT_PUMP_LIMIT 0x000000FFU #define EFUSE_PVT_PUMP_LIMIT_M (EFUSE_PVT_PUMP_LIMIT_V << EFUSE_PVT_PUMP_LIMIT_S) @@ -760,67 +761,95 @@ extern "C" { */ #define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) /** EFUSE_PUMP_DRV : RO; bitpos: [3:0]; default: 0; - * Use to configure charge pump voltage gain. + * Use to configure charge pump voltage gain.\\ */ #define EFUSE_PUMP_DRV 0x0000000FU #define EFUSE_PUMP_DRV_M (EFUSE_PUMP_DRV_V << EFUSE_PUMP_DRV_S) #define EFUSE_PUMP_DRV_V 0x0000000FU #define EFUSE_PUMP_DRV_S 0 -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:4]; default: 0; - * Represents the second 28-bit of zeroth part of system data. +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [7:4]; default: 0; + * Minor chip version */ -#define EFUSE_SYS_DATA_PART0_2 0x0FFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0x0FFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 4 +#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_S 4 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [9:8]; default: 0; + * Major chip version + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 8 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [10]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(10)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 10 +/** EFUSE_PKG_VERSION : R; bitpos: [13:11]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 11 +/** EFUSE_RESERVED_1_174 : R; bitpos: [31:14]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_174 0x0003FFFFU +#define EFUSE_RESERVED_1_174_M (EFUSE_RESERVED_1_174_V << EFUSE_RESERVED_1_174_S) +#define EFUSE_RESERVED_1_174_V 0x0003FFFFU +#define EFUSE_RESERVED_1_174_S 14 /** EFUSE_RD_SYS_PART1_DATA0_REG register * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register * Represents rd_sys_part1_data4 @@ -946,25 +975,39 @@ extern "C" { * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register * Represents rd_key0_data0 @@ -1677,6 +1720,13 @@ extern "C" { #define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) #define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U #define EFUSE_POWERGLITCH_EN_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ @@ -1726,6 +1776,20 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; * Represents the programming error of EFUSE_USB_EXCHG_PINS */ @@ -2025,143 +2089,136 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) /** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys */ #define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) #define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 /** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ #define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) #define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) #define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U #define EFUSE_RD_MAC_SYS_FAIL_S 3 /** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data */ #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 /** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ #define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) #define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) #define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 /** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data */ #define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) #define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_S 8 /** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_USR_DATA_FAIL (BIT(11)) #define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) #define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U #define EFUSE_RD_USR_DATA_FAIL_S 11 /** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data */ #define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) #define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 /** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) #define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) #define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY0_DATA_FAIL_S 15 /** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data */ #define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) #define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 /** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) #define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) #define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY1_DATA_FAIL_S 19 /** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data */ #define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) #define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 /** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) #define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) #define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY2_DATA_FAIL_S 23 /** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data */ #define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) #define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 /** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) #define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) #define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY3_DATA_FAIL_S 27 /** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data */ #define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) #define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 /** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) #define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) @@ -2173,36 +2230,34 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) /** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key5_data */ #define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) #define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 /** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) #define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) #define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY5_DATA_FAIL_S 3 /** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 /** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. */ #define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) #define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) @@ -2226,36 +2281,30 @@ extern "C" { */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power down eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Configures whether to force activate clock signal of eFuse SRAM.\\ 1: Force + * activate\\ 0: No effect\\ */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power up eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Configures whether to force enable eFuse register configuration clock signal.\\ 1: + * Force\\ 0: The clock is enabled only during the reading and writing of registers\\ */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2267,10 +2316,8 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * Configures operation command type.\\ 0x5A5A: Program operation command\\ 0x5AA5: + * Read operation command\\ Other values: No effect\\ */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) @@ -2296,15 +2343,55 @@ extern "C" { */ #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Represents the state of the eFuse state machine.\\ 0: Reset state, the initial + * state after power-up\\ 1: Idle state\\ Other values: Non-idle state\\ */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) #define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * Represents the value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * Represents the value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * Represents the value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * Represents the value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * Represents the value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * Represents the value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; * Represents the number of block valid bit. */ @@ -2332,18 +2419,14 @@ extern "C" { */ #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + * Configures whether to send read commands.\\ 1: Send\\ 0: No effect\\ */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + * Configures whether to send programming commands.\\ 1: Send\\ 0: No effect\\ */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) @@ -2461,9 +2544,8 @@ extern "C" { #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Configures whether to reduce the power supply of programming voltage.\\ 0: Not + * reduce\\ 1: Reduce\\ */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -2560,9 +2642,8 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Configures whether to bypass the Reed-Solomon (RS) correction step.\\ 0: Not + * bypass\\ 1: Bypass\\ */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) @@ -2576,9 +2657,8 @@ extern "C" { #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Configures whether to update multi-bit register signals.\\ 1: Update\\ 0: No + * effect\\ */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) diff --git a/components/soc/esp32h21/register/soc/efuse_struct.h b/components/soc/esp32h21/register/soc/efuse_struct.h index 8e7a837b28d..1bae28705ee 100644 --- a/components/soc/esp32h21/register/soc/efuse_struct.h +++ b/components/soc/esp32h21/register/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -46,9 +46,7 @@ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled.\\ 1: Disabled\\ 0: Enabled\\ */ uint32_t wr_dis:32; }; @@ -62,112 +60,102 @@ typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled.\\ 1: Disabled\\ 0: Enabled\\ */ uint32_t rd_dis:7; /** pvt_glitch_en : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1: Enable. - * 0: Disable + * Represents whether to enable PVT power glitch monitor function.\\1: Enable. \\0: + * Disable\\ */ uint32_t pvt_glitch_en:1; /** dis_icache : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. - * 1: Disabled - * 0: Enabled + * Represents whether icache is disabled or enabled.\\ 1: Disabled\\ 0: Enabled\\ */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. \\ 1: + * Disabled\\ 0: Enabled\\ */ uint32_t dis_usb_jtag:1; /** powerglitch_en : RO; bitpos: [10]; default: 0; - * Represents whether to enable power glitch function. + * Represents whether to enable power glitch function.\\ */ uint32_t powerglitch_en:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether to disable USB-Serial-JTAG.\\ + */ + uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function that forces chip into Download mode is disabled. \\ + * 1: Disabled\\ 0: Enabled\\ */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during - * boot_mode_download. - * 1: Disabled - * 0: Enabled + * boot_mode_download.\\ 1: Disabled\\ 0: Enabled\\ */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether TWAI function is disabled. \\ 1: Disabled\\ 0: Enabled\\ */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; * Represents whether the selection of a JTAG signal source through the strapping pin * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured - * to 0. For more information, please refer to Chapter Placeholder. - * 1: Enabled - * 0: Disabled + * to 0. For more information, please refer to Chapter Placeholder.\\ 1: Enabled\\ 0: + * Disabled\\ */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled + * HMAC. \\ Odd count of bits with a value of 1: Disabled\\ Even count of bits with a + * value of 1: Enabled\\ */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled + * Represents whether PAD JTAG is disabled in the hard way (permanently).\\ 1: + * Disabled\\ 0: Enabled\\ */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled + * Represents whether flash encryption is disabled (except in SPI boot mode).\\ 1: + * Disabled\\ 0: Enabled\\ */ uint32_t dis_download_manual_encrypt:1; - uint32_t reserved_21:4; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, + * stored in eFuse.\\ + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse.\\ + */ + uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged + * Represents whether the D+ and D- pins is exchanged.\\ 1: Exchanged\\ 0: Not + * exchanged\\ */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. - * 1: Functioned - * 0: Not functioned + * Represents whether vdd spi pin is functioned as gpio.\\ 1: Functioned\\ 0: Not + * functioned\\ */ uint32_t vdd_spi_as_gpio:1; /** ecdsa_curve_mode : RO; bitpos: [28:27]; default: 0; - * Represents the configuration of the curve of ECDSA calculation. - * 0: Only enable P256 - * 1: Only enable P192 - * 2: Both enable P256 and P192 - * 3: Only enable P256 + * Represents the configuration of the curve of ECDSA calculation.\\ 0: Only enable + * P256\\ 1: Only enable P192\\ 2: Both enable P256 and P192\\ 3: Only enable P256\\ */ uint32_t ecdsa_curve_mode:2; /** ecc_force_const_time : RO; bitpos: [29]; default: 0; - * Represents whether to permanently turn on ECC const-time mode. - * 0: Disabled - * 1: Enabled + * Represents whether to permanently turn on ECC const-time mode.\\ 0: Disabled\\ 1: + * Enabled\\ */ uint32_t ecc_force_const_time:1; /** xts_dpa_pseudo_level : RO; bitpos: [31:30]; default: 0; - * Represents control method of xts pseudo-round anti-dpa attack function. - * 0: Controlled by register - * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation. + * Represents control method of xts pseudo-round anti-dpa attack function.\\ 0: + * Controlled by register\\ 1-3: The higher the value is, the more pseudo-rounds are + * inserted to the xts-aes calculation.\\ */ uint32_t xts_dpa_pseudo_level:2; }; @@ -180,51 +168,45 @@ typedef union { typedef union { struct { /** io_ldo_adjust : RO; bitpos: [7:0]; default: 0; - * Represents configuration of IO LDO mode and voltage. + * Represents configuration of IO LDO mode and voltage.\\ */ uint32_t io_ldo_adjust:8; /** vdd_spi_ldo_adjust : RO; bitpos: [15:8]; default: 0; - * Represents configuration of FLASH LDO mode and voltage. + * Represents configuration of FLASH LDO mode and voltage.\\ */ uint32_t vdd_spi_ldo_adjust:8; /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0：The originally configured STG0 threshold × 2 - * 1：The originally configured STG0 threshold × 4 - * 2：The originally configured STG0 threshold × 8 - * 3：The originally configured STG0 threshold × 16 + * Represents RTC watchdog timeout threshold. 0: The originally configured STG0 + * threshold x 2 1: The originally configured STG0 threshold x 4 2: The originally + * configured STG0 threshold x 8 3: The originally configured STG0 threshold x 16 */ uint32_t wdt_delay_sel:2; /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled + * Represents whether SPI boot encryption/decryption is enabled. \\ Odd count of bits + * with a value of 1: Enabled\\ Even count of bits with a value of 1: Disabled\\ */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key 0 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking Secure Boot key 0 is enabled. \\ 1: Enabled\\ 0: + * Disabled\\ */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking Secure Boot key 1 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking Secure Boot key 1 is enabled. \\ 1: Enabled\\ 0: + * Disabled\\ */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking Secure Boot key 2 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking Secure Boot key 2 is enabled. \\ 1: Enabled\\ 0: + * Disabled\\ */ uint32_t secure_boot_key_revoke2:1; /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. See Table tab:efuse-key-purpose. + * Represents the purpose of Key0. See Table tab:efuse-key-purpose.\\ */ uint32_t key_purpose_0:4; /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. See Table tab:efuse-key-purpose. + * Represents the purpose of Key1. See Table tab:efuse-key-purpose.\\ */ uint32_t key_purpose_1:4; }; @@ -237,58 +219,49 @@ typedef union { typedef union { struct { /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. See Table tab:efuse-key-purpose. + * Represents the purpose of Key2. See Table tab:efuse-key-purpose.\\ */ uint32_t key_purpose_2:4; /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. See Table tab:efuse-key-purpose. + * Represents the purpose of Key3. See Table tab:efuse-key-purpose.\\ */ uint32_t key_purpose_3:4; /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. See Table tab:efuse-key-purpose. + * Represents the purpose of Key4. See Table tab:efuse-key-purpose.\\ */ uint32_t key_purpose_4:4; /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. See Table tab:efuse-key-purpose. + * Represents the purpose of Key5. See Table tab:efuse-key-purpose.\\ */ uint32_t key_purpose_5:4; /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC_DPA_OFF - * 1: Security level is SEC_DPA_LOW - * 2: Security level is SEC_DPA_MIDDLE - * 3: Security level is SEC_DPA_HIGH - * For more information, please refer to Chapter mod:sysreg > Section - * sec:sysreg-anti-dpa-attack-security-control. + * configuring the clock random frequency division mode.\\ 0: Security level is + * SEC_DPA_OFF\\ 1: Security level is SEC_DPA_LOW\\ 2: Security level is + * SEC_DPA_MIDDLE\\ 3: Security level is SEC_DPA_HIGH\\ For more information, please + * refer to Chapter mod:sysreg > Section sec:sysreg-anti-dpa-attack-security-control.\\ */ uint32_t sec_dpa_level:2; /** io_ldo_1p8 : RO; bitpos: [18]; default: 0; - * Represents select IO LDO voltage to 1.8V or 3.3V. - * 1: 1.8V - * 0: 3.3V + * Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V\\ */ uint32_t io_ldo_1p8:1; /** crypt_dpa_enable : RO; bitpos: [19]; default: 0; - * Represents whether defense against DPA attack is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether defense against DPA attack is enabled.\\ 1: Enabled\\ 0: + * Disabled\\ */ uint32_t crypt_dpa_enable:1; /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether Secure Boot is enabled.\\ 1: Enabled\\ 0: Disabled\\ */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether aggressive revocation of Secure Boot is enabled.\\ 1: Enabled\\ + * 0: Disabled\\ */ uint32_t secure_boot_aggressive_revoke:1; /** powerglitch_en1 : RO; bitpos: [26:22]; default: 0; - * Represents whether to enable power glitch function when chip power on. + * Represents whether to enable power glitch function when chip power on.\\ */ uint32_t powerglitch_en1:5; /** dcdc_ccm_en : RO; bitpos: [27]; default: 0; @@ -296,9 +269,9 @@ typedef union { */ uint32_t dcdc_ccm_en:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. - * When the value is less than 15, the waiting time is the programmed value. - * Otherwise, the waiting time is a fixed value, i.e. 30 ms. + * Represents the flash waiting time after power-up. Measurement unit: ms.\\ When the + * value is less than 15, the waiting time is the programmed value. Otherwise, the + * waiting time is a fixed value, i.e. 30 ms.\\ */ uint32_t flash_tpuw:4; }; @@ -311,71 +284,57 @@ typedef union { typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether all download modes are disabled. - * 1: Disabled - * 0: Enabled + * Represents whether all download modes are disabled.\\ 1: Disabled\\ 0: Enabled\\ */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether direct boot mode is disabled.\\ 1: Disabled\\ 0: Enabled\\ */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether print from USB-Serial-JTAG during ROM boot is disabled.\\ 1: + * Disabled\\ 0: Enabled\\ */ uint32_t dis_usb_serial_jtag_rom_print:1; /** flash_ldo_efuse_sel : RO; bitpos: [3]; default: 0; - * Represents whether to select efuse control flash ldo default voltage. - * 1: efuse - * 0: strapping + * Represents whether to select efuse control flash ldo default voltage. \\1: + * efuse\\0: strapping\\ */ uint32_t flash_ldo_efuse_sel:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-Serial-JTAG download function is disabled.\\ 1: + * Disabled\\ 0: Enabled\\ */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [5]; default: 0; * Represents whether security download is enabled. Only UART is supported for * download. Reading/writing RAM or registers is not supported (i.e. Stub download is - * not supported). - * 1: Enabled - * 0: Disabled + * not supported).\\ 1: Enabled\\ 0: Disabled\\ */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO8 is reset at low level. - * 2: Enable printing when GPIO8 is reset at high level. - * 3: Force disable printing. + * Represents the type of UART printing.\\ 0: Force enable printing.\\ 1: Enable + * printing when GPIO8 is reset at low level.\\ 2: Enable printing when GPIO8 is reset + * at high level.\\ 3: Force disable printing.\\ */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced - * 0: Not forced + * Represents whether ROM code is forced to send a resume command during SPI boot.\\ + * 1: Forced\\ 0: Not forced\\ */ uint32_t force_send_resume:1; /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the security version used by ESP-IDF anti-rollback feature. + * Represents the security version used by ESP-IDF anti-rollback feature.\\ */ uint32_t secure_version:16; /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled.\\ + * 1: Disabled\\ 0: Enabled\\ */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; - * Represents whether to enable the hysteresis function of pad 0-5. - * 0: Disabled - * 1: Enabled + * Represents whether to enable the hysteresis function of pad 0-5.\\ 0: Disabled\\ 1: + * Enabled\\ */ uint32_t hys_en_pad0:6; }; @@ -388,15 +347,12 @@ typedef union { typedef union { struct { /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; - * Represents whether to enable the hysteresis function of pad 6-27. - * 0: Disabled - * 1: Enabled + * Represents whether to enable the hysteresis function of pad 6-27.\\ 0: Disabled\\ + * 1: Enabled\\ */ uint32_t hys_en_pad1:22; /** flash_ldo_power_sel : RO; bitpos: [22]; default: 0; - * Represents which flash LDO is selected. - * 0: FLASH LDO 1P8. - * 1: FLASH LDO 1P2. + * Represents which flash LDO is selected.\\ 0: FLASH LDO 1P8.\\ 1: FLASH LDO 1P2.\\ */ uint32_t flash_ldo_power_sel:1; uint32_t reserved_23:9; @@ -406,8 +362,8 @@ typedef union { /** Group: block1 registers */ -/** Type of rd_mac_sys_0 register - * Represents rd_mac_sys_ +/** Type of rd_mac_sys0 register + * Represents rd_mac_sys */ typedef union { struct { @@ -419,8 +375,8 @@ typedef union { uint32_t val; } efuse_rd_mac_sys0_reg_t; -/** Type of rd_mac_sys_1 register - * Represents rd_mac_sys_ +/** Type of rd_mac_sys1 register + * Represents rd_mac_sys */ typedef union { struct { @@ -436,8 +392,8 @@ typedef union { uint32_t val; } efuse_rd_mac_sys1_reg_t; -/** Type of rd_mac_sys_2 register - * Represents rd_mac_sys_ +/** Type of rd_mac_sys2 register + * Represents rd_mac_sys */ typedef union { struct { @@ -453,8 +409,8 @@ typedef union { uint32_t val; } efuse_rd_mac_sys2_reg_t; -/** Type of rd_mac_sys_3 register - * Represents rd_mac_sys_ +/** Type of rd_mac_sys3 register + * Represents rd_mac_sys */ typedef union { struct { @@ -463,95 +419,320 @@ typedef union { */ uint32_t mac_reserved_2:4; /** pvt_cell_select : RO; bitpos: [10:4]; default: 0; - * Represents the selection of Power glitch monitor PVT cell. + * Represents the selection of Power glitch monitor PVT cell.\\ */ uint32_t pvt_cell_select:7; /** mac_reserved_3 : RO; bitpos: [17:11]; default: 0; * Reserved. */ uint32_t mac_reserved_3:7; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. + /** blk_version_minor : R; bitpos: [20:18]; default: 0; + * Minor version of BLOCK2 */ - uint32_t sys_data_part0_0:14; + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [22:21]; default: 0; + * Major version of BLOCK2 + */ + uint32_t blk_version_major:2; + /** disable_blk_version_major : R; bitpos: [23]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** flash_cap : R; bitpos: [26:24]; default: 0; + * Mark the capacity of in-package Flash + */ + uint32_t flash_cap:3; + /** flash_vendor : R; bitpos: [29:27]; default: 0; + * Mark the vendor of in-package Flash + */ + uint32_t flash_vendor:3; + /** temp : R; bitpos: [31:30]; default: 0; + * Mark the specified maximum ambient temperature that ESP Chip can work properly + */ + uint32_t temp:2; }; uint32_t val; } efuse_rd_mac_sys3_reg_t; -/** Type of rd_mac_sys_4 register - * Represents rd_mac_sys_ +/** Type of rd_mac_sys4 register + * Represents rd_mac_sys */ typedef union { struct { uint32_t reserved_0:5; /** pvt_limit : RO; bitpos: [20:5]; default: 0; - * Represents the threshold of power glitch monitor. + * Represents the threshold of power glitch monitor.\\ */ uint32_t pvt_limit:16; /** pvt_glitch_charge_reset : RO; bitpos: [21]; default: 0; - * Represents whether to trigger reset or charge pump when PVT power glitch happened. - * 1:Trigger charge pump. - * 0:Trigger reset + * Represents whether to trigger reset or charge pump when PVT power glitch + * happened.\\ 1:Trigger charge pump. \\ 0:Trigger reset\\ */ uint32_t pvt_glitch_charge_reset:1; /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0; - * Represents the configuration of glitch mode. + * Represents the configuration of glitch mode.\\ */ uint32_t pvt_glitch_mode:2; /** pvt_pump_limit : RO; bitpos: [31:24]; default: 0; - * Represents the configuration voltage monitor limit for charge pump. + * Represents the configuration voltage monitor limit for charge pump.\\ */ uint32_t pvt_pump_limit:8; }; uint32_t val; } efuse_rd_mac_sys4_reg_t; -/** Type of rd_mac_sys_5 register - * Represents rd_mac_sys_ +/** Type of rd_mac_sys5 register + * Represents rd_mac_sys */ typedef union { struct { /** pump_drv : RO; bitpos: [3:0]; default: 0; - * Use to configure charge pump voltage gain. + * Use to configure charge pump voltage gain.\\ */ uint32_t pump_drv:4; - /** sys_data_part0_2 : RO; bitpos: [31:4]; default: 0; - * Represents the second 28-bit of zeroth part of system data. + /** wafer_version_minor : R; bitpos: [7:4]; default: 0; + * Minor chip version */ - uint32_t sys_data_part0_2:28; + uint32_t wafer_version_minor:4; + /** wafer_version_major : R; bitpos: [9:8]; default: 0; + * Major chip version + */ + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : R; bitpos: [10]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** pkg_version : R; bitpos: [13:11]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** reserved_1_174 : R; bitpos: [31:14]; default: 0; + * reserved + */ + uint32_t reserved_1_174:18; }; uint32_t val; } efuse_rd_mac_sys5_reg_t; /** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_sys_part1_data0 register + * Represents rd_sys_part1_data0 */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_n:32; + uint32_t optional_unique_id:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Represents rd_sys_part1_data1 + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Represents rd_sys_part1_data2 + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Represents rd_sys_part1_data3 + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Represents rd_sys_part1_data4 + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Represents rd_sys_part1_data5 + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Represents rd_sys_part1_data6 + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Represents rd_sys_part1_data7 + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; /** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan +/** Type of rd_usr_data0 register + * Represents rd_usr_data0 */ typedef union { struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; + /** usr_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ - uint32_t usr_datan:32; + uint32_t usr_data0:32; }; uint32_t val; -} efuse_rd_usr_datan_reg_t; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Represents rd_usr_data1 + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Represents rd_usr_data2 + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Represents rd_usr_data3 + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Represents rd_usr_data4 + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Represents rd_usr_data5 + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Represents rd_usr_data6 + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Represents rd_usr_data7 + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; /** Group: block4 registers */ @@ -685,7 +866,10 @@ typedef union { * Represents the programming error of EFUSE_POWERGLITCH_EN */ uint32_t powerglitch_en_err:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ + uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ @@ -714,7 +898,14 @@ typedef union { * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ uint32_t dis_download_manual_encrypt_err:1; - uint32_t reserved_21:4; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + */ + uint32_t usb_drefl_err:2; /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; * Represents the programming error of EFUSE_USB_EXCHG_PINS */ @@ -919,99 +1110,92 @@ typedef union { */ typedef union { struct { - /** rd_mac_sys__err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys_ + /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys */ - uint32_t rd_mac_sys__err_num:3; - /** rd_mac_sys__fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys_ is reliable - * 1: Means that programming rd_mac_sys_ failed and the number of error bytes is over 6. + uint32_t rd_mac_sys_err_num:3; + /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ - uint32_t rd_mac_sys__fail:1; + uint32_t rd_mac_sys_fail:1; /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data */ uint32_t rd_sys_part1_data_err_num:3; /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ uint32_t rd_sys_part1_data_fail:1; /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data */ uint32_t rd_usr_data_err_num:3; /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. */ uint32_t rd_usr_data_fail:1; /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data */ uint32_t rd_key0_data_err_num:3; /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key0_data_fail:1; /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data */ uint32_t rd_key1_data_err_num:3; /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key1_data_fail:1; /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data */ uint32_t rd_key2_data_err_num:3; /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key2_data_fail:1; /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data */ uint32_t rd_key3_data_err_num:3; /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key3_data_fail:1; /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data */ uint32_t rd_key4_data_err_num:3; /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key4_data_fail:1; }; @@ -1024,27 +1208,25 @@ typedef union { typedef union { struct { /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key5_data */ uint32_t rd_key5_data_err_num:3; /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key5_data_fail:1; /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data */ uint32_t rd_sys_part2_data_err_num:3; /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. */ uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_8:24; @@ -1076,28 +1258,22 @@ typedef union { typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power down eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Configures whether to force activate clock signal of eFuse SRAM.\\ 1: Force + * activate\\ 0: No effect\\ */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power up eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Configures whether to force enable eFuse register configuration clock signal.\\ 1: + * Force\\ 0: The clock is enabled only during the reading and writing of registers\\ */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -1113,10 +1289,8 @@ typedef union { typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * Configures operation command type.\\ 0x5A5A: Program operation command\\ 0x5AA5: + * Read operation command\\ Other values: No effect\\ */ uint32_t op_code:16; /** cfg_ecdsa_l_blk : R/W; bitpos: [19:16]; default: 0; @@ -1151,9 +1325,8 @@ typedef union { */ uint32_t dac_num:8; /** oe_clr : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Configures whether to reduce the power supply of programming voltage.\\ 0: Not + * reduce\\ 1: Reduce\\ */ uint32_t oe_clr:1; uint32_t reserved_18:14; @@ -1237,9 +1410,8 @@ typedef union { typedef union { struct { /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Configures whether to bypass the Reed-Solomon (RS) correction step.\\ 0: Not + * bypass\\ 1: Bypass\\ */ uint32_t bypass_rs_correction:1; /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; @@ -1247,9 +1419,8 @@ typedef union { */ uint32_t bypass_rs_blk_num:11; /** update : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Configures whether to update multi-bit register signals.\\ 1: Update\\ 0: No + * effect\\ */ uint32_t update:1; /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; @@ -1270,13 +1441,34 @@ typedef union { typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Represents the state of the eFuse state machine.\\ 0: Reset state, the initial + * state after power-up\\ 1: Idle state\\ Other values: Non-idle state\\ */ uint32_t state:4; - uint32_t reserved_4:6; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * Represents the value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * Represents the value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * Represents the value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * Represents the value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * Represents the value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * Represents the value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; * Represents the number of block valid bit. */ @@ -1302,15 +1494,11 @@ typedef union { typedef union { struct { /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + * Configures whether to send read commands.\\ 1: Send\\ 0: No effect\\ */ uint32_t read_cmd:1; /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + * Configures whether to send programming commands.\\ 1: Send\\ 0: No effect\\ */ uint32_t pgm_cmd:1; /** blk_num : R/W; bitpos: [5:2]; default: 0; @@ -1407,14 +1595,28 @@ typedef struct { volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys0_reg_t rd_mac_sys_0; - volatile efuse_rd_mac_sys1_reg_t rd_mac_sys_1; - volatile efuse_rd_mac_sys2_reg_t rd_mac_sys_2; - volatile efuse_rd_mac_sys3_reg_t rd_mac_sys_3; - volatile efuse_rd_mac_sys4_reg_t rd_mac_sys_4; - volatile efuse_rd_mac_sys5_reg_t rd_mac_sys_5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];