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feat(sdm): add sleep retention support

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This commit is contained in:
morris
2025-08-11 10:15:40 +08:00
parent 83512e3e7c
commit f808fb9eaf
27 changed files with 346 additions and 5 deletions
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components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
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@@ -767,6 +767,10 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_ANA_CMPR_NUM
int
default 2
components/soc/esp32p4/include/soc/retention_periph_defs.h
+2
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@@ -59,6 +59,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_LEDC = 33,
SLEEP_RETENTION_MODULE_MCPWM0 = 34,
SLEEP_RETENTION_MODULE_MCPWM1 = 35,
SLEEP_RETENTION_MODULE_SDM0 = 36,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
@@ -100,6 +101,7 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \
: ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_MCPWM1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \
: false)
#ifdef __cplusplus
components/soc/esp32p4/include/soc/soc_caps.h
+2
View File
@@ -298,6 +298,8 @@
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*------------------------- Analog Comparator CAPS ---------------------------*/
#define SOC_ANA_CMPR_NUM (2)
#define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE (1) // Support positive/negative/any cross interrupt
components/soc/esp32p4/sdm_periph.c
+30
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@@ -6,6 +6,7 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/gpio_ext_reg.h"
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
@@ -38,3 +39,32 @@ const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
}
}
};
/**
* @brief Registers in retention context:
* GPIO_EXT_SIGMADELTA[x]_REG
* GPIO_EXT_SIGMADELTA_MISC_REG
*/
#define GPIO_EXT_RETENTION_REGS_CNT 9
#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x0)
static const uint32_t gpio_ext_regs_map[4] = {0x2ff, 0x0, 0x0, 0x0};
static const regdma_entries_config_t gpio_ext_regdma_entries[] = {
// backup stage: save configuration and status registers
// restore stage: restore the configuration and status registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_SDM_LINK(0x00),
GPIO_EXT_RETENTION_REGS_BASE, GPIO_EXT_RETENTION_REGS_BASE,
GPIO_EXT_RETENTION_REGS_CNT, 0, 0,
gpio_ext_regs_map[0], gpio_ext_regs_map[1],
gpio_ext_regs_map[2], gpio_ext_regs_map[3]),
.owner = ENTRY(0),
},
};
const soc_sdm_retention_desc_t soc_sdm_retention_infos[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_SDM0,
.regdma_entry_array = gpio_ext_regdma_entries,
.array_size = ARRAY_SIZE(gpio_ext_regdma_entries)
}
};