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refactor(dac): move DMA interrupt handling behind dac_priv_dma callbacks
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -347,16 +347,18 @@ typedef enum {
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/**
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* @brief Array initializer for all supported clock sources of DAC digital controller
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*/
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#define SOC_DAC_DIGI_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL}
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#define SOC_DAC_DIGI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_APLL}
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/**
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* @brief DAC digital controller clock source
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*
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* @note The ESP32 DAC DMA is based on I2S and uses the same clock source as I2S.
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*/
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typedef enum {
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DAC_DIGI_CLK_SRC_PLLD2 = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock */
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DAC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
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DAC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the default source clock */
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DAC_DIGI_CLK_SRC_PLLD2 [[deprecated("use DAC_DIGI_CLK_SRC_PLL_160M instead")]] = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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DAC_DIGI_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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DAC_DIGI_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
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DAC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
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} soc_periph_dac_digi_clk_src_t;
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/**
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