diff --git a/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h b/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h
index 7a42801cd76..4a6aa116352 100644
--- a/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h
+++ b/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h
@@ -128,30 +128,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src)
         cam_ll_select_clk_src(__VA_ARGS__); \
     } while(0)
 
-/**
- * @brief  Get the CAM source clock type
- *
- * @param dev CAM register base address
- * @param src The pointer to accept the CAM source clock type
- */
-static inline void cam_ll_get_clk_src(lcd_cam_dev_t *dev, cam_clock_source_t *src)
-{
-    switch (HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel) {
-    case 0:
-        *src = CAM_CLK_SRC_XTAL;
-        break;
-    case 1:
-        *src = CAM_CLK_SRC_PLL160M;
-        break;
-    case 2:
-        *src = CAM_CLK_SRC_APLL;
-        break;
-    default:
-        HAL_ASSERT(false);
-        break;
-    }
-}
-
 /**
  * @brief Set clock coefficient of CAM peripheral
  *
diff --git a/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h b/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h
index 2b58c45f76f..16665fde5d4 100644
--- a/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h
+++ b/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h
@@ -99,30 +99,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src)
     }
 }
 
-/**
- * @brief  Get the CAM source clock type
- *
- * @param dev CAM register base address
- * @param src The pointer to accept the CAM source clock type
- */
-static inline void cam_ll_get_clk_src(lcd_cam_dev_t *dev, cam_clock_source_t *src)
-{
-    switch (LCD_CAM.cam_ctrl.cam_clk_sel) {
-    case 1:
-        *src = CAM_CLK_SRC_XTAL;
-        break;
-    case 2:
-        *src = CAM_CLK_SRC_PLL240M;
-        break;
-    case 3:
-        *src = CAM_CLK_SRC_PLL160M;
-        break;
-    default:
-        HAL_ASSERT(false);
-        break;
-    }
-}
-
 /**
  * @brief Set clock coefficient of CAM peripheral
  *
diff --git a/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h b/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h
index 2bb647532f4..6043b2d4850 100644
--- a/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h
+++ b/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h
@@ -104,31 +104,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src)
     }
 }
 
-/**
- * @brief  Get the CAM source clock type
- *
- * @param dev CAM register base address
- * @param src The pointer to accept the CAM source clock type
- */
-static inline void cam_ll_get_clk_src(lcd_cam_dev_t *dev, cam_clock_source_t *src)
-{
-    (void)dev;
-    switch (HP_SYS_CLKRST.lcdcam_cam_ctrl0.reg_cam_clk_src_sel) {
-    case 0:
-        *src = CAM_CLK_SRC_XTAL;
-        break;
-    case 1:
-        *src = CAM_CLK_SRC_PLL160M;
-        break;
-    case 2:
-        *src = CAM_CLK_SRC_APLL;
-        break;
-    default:
-        HAL_ASSERT(false);
-        break;
-    }
-}
-
 /**
  * @brief Set clock coefficient of CAM peripheral
  *
diff --git a/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h b/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h
index 443e61be6b8..2984647ff9e 100644
--- a/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h
+++ b/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h
@@ -662,14 +662,14 @@ static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool
 }
 
 /**
- * @brief Set cycle of delay for DC line
+ * @brief Set delay mode for DC line
  *
  * @param dev LCD register base address
- * @param delay Ticks of delay
+ * @param mode Delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay)
+static inline void lcd_ll_set_dc_delay_mode(lcd_cam_dev_t *dev, uint32_t mode)
 {
-    dev->lcd_dly_mode_cfg1.lcd_cd_mode = delay;
+    dev->lcd_dly_mode_cfg1.lcd_cd_mode = mode;
 }
 
 /**
@@ -789,18 +789,38 @@ static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_lev
 }
 
 /**
- * @brief Set extra delay for HSYNC, VSYNC, and DE signals
+ * @brief Set delay mode for HSYNC, VSYNC, and DE signals
  *
  * @param dev LCD register base address
- * @param hsync_delay HSYNC delay
- * @param vsync_delay VSYNC delay
- * @param de_delay DE delay
+ * @param hsync_mode HSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ * @param vsync_mode VSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ * @param de_mode DE delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay)
+static inline void lcd_ll_set_delay_mode(lcd_cam_dev_t *dev, uint32_t hsync_mode, uint32_t vsync_mode, uint32_t de_mode)
 {
-    dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_delay;
-    dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_delay;
-    dev->lcd_dly_mode_cfg1.lcd_de_mode = de_delay;
+    dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_mode;
+    dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_mode;
+    dev->lcd_dly_mode_cfg1.lcd_de_mode = de_mode;
+}
+
+/**
+ * @brief Set delay mode for all data lines
+ *
+ * @param dev LCD register base address
+ * @param mode Data line delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ */
+static inline void lcd_ll_set_data_delay_mode(lcd_cam_dev_t *dev, uint32_t mode)
+{
+    uint32_t reg_val = 0;
+    for (int i = 0; i < 16; i++) {
+        reg_val |= (mode & 0x03) << (2 * i);
+    }
+    dev->lcd_dly_mode_cfg2.val = reg_val;
+    reg_val = 0;
+    for (int i = 0; i < 8; i++) {
+        reg_val |= (mode & 0x03) << (2 * i);
+    }
+    dev->lcd_dly_mode_cfg1.val = (dev->lcd_dly_mode_cfg1.val & 0xFFFF0000) | reg_val;
 }
 
 /**
diff --git a/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h b/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h
index 6164ddf39c7..001868f2484 100644
--- a/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h
+++ b/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h
@@ -617,14 +617,14 @@ static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool
 }
 
 /**
- * @brief Set cycle of delay for DC line
+ * @brief Set delay mode for DC line
  *
  * @param dev LCD register base address
- * @param delay Ticks of delay
+ * @param mode Delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay)
+static inline void lcd_ll_set_dc_delay_mode(lcd_cam_dev_t *dev, uint32_t mode)
 {
-    dev->lcd_dly_mode.lcd_cd_mode = delay;
+    dev->lcd_dly_mode.lcd_cd_mode = mode;
 }
 
 /**
@@ -741,31 +741,31 @@ static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_lev
 }
 
 /**
- * @brief Set extra delay for HSYNC, VSYNC, and DE signals
+ * @brief Set delay mode for HSYNC, VSYNC, and DE signals
  *
  * @param dev LCD register base address
- * @param hsync_delay HSYNC delay
- * @param vsync_delay VSYNC delay
- * @param de_delay DE delay
+ * @param hsync_mode HSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ * @param vsync_mode VSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ * @param de_mode DE delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay)
+static inline void lcd_ll_set_delay_mode(lcd_cam_dev_t *dev, uint32_t hsync_mode, uint32_t vsync_mode, uint32_t de_mode)
 {
-    dev->lcd_dly_mode.lcd_hsync_mode = hsync_delay;
-    dev->lcd_dly_mode.lcd_vsync_mode = vsync_delay;
-    dev->lcd_dly_mode.lcd_de_mode = de_delay;
+    dev->lcd_dly_mode.lcd_hsync_mode = hsync_mode;
+    dev->lcd_dly_mode.lcd_vsync_mode = vsync_mode;
+    dev->lcd_dly_mode.lcd_de_mode = de_mode;
 }
 
 /**
- * @brief Set extra delay for data lines
+ * @brief Set delay mode for all data lines
  *
  * @param dev LCD register base address
- * @param delay Data line delay
+ * @param mode Data line delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_data_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay)
+static inline void lcd_ll_set_data_delay_mode(lcd_cam_dev_t *dev, uint32_t mode)
 {
     uint32_t reg_val = 0;
     for (int i = 0; i < 16; i++) {
-        reg_val |= (delay & 0x03) << (2 * i);
+        reg_val |= (mode & 0x03) << (2 * i);
     }
     dev->lcd_data_dout_mode.val = reg_val;
 }
diff --git a/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h b/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h
index 7fc969ce91c..ea2b43500ba 100644
--- a/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h
+++ b/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h
@@ -214,7 +214,8 @@ static inline void lcd_ll_mem_set_low_power_mode(lcd_cam_dev_t *dev, lcd_ll_mem_
 /**
  * @brief Enable the transfer buffer(memory block) for LCD module
  *
- * @note Only for RGB mode
+ * @note Only for RGB mode, and can't work with YUV420 color convert mode.
+ *
  * @param dev Peripheral instance address
  * @param en True to enable, False to disable
  */
@@ -652,14 +653,14 @@ static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool
 }
 
 /**
- * @brief Set cycle of delay for DC line
+ * @brief Set delay mode for DC line
  *
  * @param dev LCD register base address
- * @param delay Ticks of delay
+ * @param mode Delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay)
+static inline void lcd_ll_set_dc_delay_mode(lcd_cam_dev_t *dev, uint32_t mode)
 {
-    dev->lcd_dly_mode_cfg1.lcd_cd_mode = delay;
+    dev->lcd_dly_mode_cfg1.lcd_cd_mode = mode;
 }
 
 /**
@@ -779,18 +780,38 @@ static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_lev
 }
 
 /**
- * @brief Set extra delay for HSYNC, VSYNC, and DE signals
+ * @brief Set delay mode for HSYNC, VSYNC, and DE signals
  *
  * @param dev LCD register base address
- * @param hsync_delay HSYNC delay
- * @param vsync_delay VSYNC delay
- * @param de_delay DE delay
+ * @param hsync_mode HSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ * @param vsync_mode VSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ * @param de_mode DE delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
  */
-static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay)
+static inline void lcd_ll_set_delay_mode(lcd_cam_dev_t *dev, uint32_t hsync_mode, uint32_t vsync_mode, uint32_t de_mode)
 {
-    dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_delay;
-    dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_delay;
-    dev->lcd_dly_mode_cfg1.lcd_de_mode = de_delay;
+    dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_mode;
+    dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_mode;
+    dev->lcd_dly_mode_cfg1.lcd_de_mode = de_mode;
+}
+
+/**
+ * @brief Set delay mode for all data lines
+ *
+ * @param dev LCD register base address
+ * @param mode Data line delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge
+ */
+static inline void lcd_ll_set_data_delay_mode(lcd_cam_dev_t *dev, uint32_t mode)
+{
+    uint32_t reg_val = 0;
+    for (int i = 0; i < 16; i++) {
+        reg_val |= (mode & 0x03) << (2 * i);
+    }
+    dev->lcd_dly_mode_cfg2.val = reg_val;
+    reg_val = 0;
+    for (int i = 0; i < 8; i++) {
+        reg_val |= (mode & 0x03) << (2 * i);
+    }
+    dev->lcd_dly_mode_cfg1.val = (dev->lcd_dly_mode_cfg1.val & 0xFFFF0000) | reg_val;
 }
 
 /**