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feat(pm): select XTAL for HP dig_sysclk in modem state

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On ESP32-S31, SOC and modem APB are decoupled, so the digital
system can run from XTAL while the modem domain stays in modem state.
This commit is contained in:
sibeibei
2026-06-10 20:41:47 +08:00
committed by yinqingzhao
parent 0c1394214f
commit f7a2fc94a6
5 changed files with 8 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/port/esp32s31/pmu_param.c
+1
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@@ -150,6 +150,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod
.icg_sysclk_en = 1, \ .icg_sysclk_en = 1, \
.sysclk_slp_sel = 1, \ .sysclk_slp_sel = 1, \
.icg_slp_sel = 1, \ .icg_slp_sel = 1, \
/* Default: dig_sysclk uses XTAL. For PLL, update divider coeffs and release PLL lock. */ \
.dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \ .dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \
} \ } \
} }
components/esp_hw_support/port/esp32s31/pmu_sleep.c
-5
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@@ -330,11 +330,6 @@ static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_confi
pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle); pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
} }
bool pmu_sleep_pll_already_enabled(void)
{
return (pmu_ll_get_sysclk_sleep_select_state(PMU_instance()->hal->dev) != 0);
}
void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp) void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
{ {
assert(PMU_instance()); assert(PMU_instance());
components/esp_hw_support/sleep_modes.c
+1 -1
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@@ -1182,7 +1182,7 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t cl
} }
#endif #endif
// Restore CPU frequency // Restore CPU frequency
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && !SOC_PM_BBPLL_PD_IN_MODEM_STATE #if SOC_PM_SUPPORT_PMU_MODEM_STATE && !SOC_PM_BBPLL_PD_IN_MODEM_STATE && !SOC_PM_MODEM_STATE_USE_XTAL
if (pmu_sleep_pll_already_enabled()) { if (pmu_sleep_pll_already_enabled()) {
rtc_clk_cpu_freq_to_pll_and_pll_lock_release(esp_pm_impl_get_cpu_freq(PM_MODE_CPU_MAX)); rtc_clk_cpu_freq_to_pll_and_pll_lock_release(esp_pm_impl_get_cpu_freq(PM_MODE_CPU_MAX));
} else } else
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
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@@ -1547,6 +1547,10 @@ config SOC_PM_SUPPORT_PMU_MODEM_STATE
bool bool
default y default y
config SOC_PM_MODEM_STATE_USE_XTAL
bool
default y
config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
bool bool
default y default y
components/soc/esp32s31/include/soc/soc_caps.h
+2
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@@ -574,6 +574,8 @@
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
/* Since SOC APB and MODEM APB on ESP32-S31 are decoupled, XTAL can be used as SOC clock in modem state */
#define SOC_PM_MODEM_STATE_USE_XTAL (1)
/* /*
* min_slp_val is derived from slow clock period (450us / slow_clk). * min_slp_val is derived from slow clock period (450us / slow_clk).