Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(fast_gpio): support CPU controlled fast GPIO driver on esp32p4

Browse Source
This commit is contained in:
morris
2024-03-22 17:13:19 +08:00
parent 573bd1bcc9
commit f71044c877
13 changed files with 156 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_gpio/test_apps/gpio_extensions/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c
+13 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -146,7 +146,11 @@ TEST_CASE("Dedicated_GPIO_run_on_multiple_CPU_cores", "[dedic_gpio]")
TaskHandle_t task_handle[SOC_CPU_CORES_NUM];
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
#if CONFIG_IDF_TARGET_ESP32P4
int start_gpio = i * TEST_GPIO_GROUP_SIZE + 20;
#else
int start_gpio = i * TEST_GPIO_GROUP_SIZE;
#endif
test_dedic_task_context_t isr_ctx = {
.sem = sem,
.gpios = {start_gpio, start_gpio + 1, start_gpio + 2, start_gpio + 3}
@@ -181,7 +185,11 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]")
SemaphoreHandle_t sem = xSemaphoreCreateBinary();
// configure GPIO
#if CONFIG_IDF_TARGET_ESP32P4
const int bundle_gpios[] = {20, 21};
#else
const int bundle_gpios[] = {0, 1};
#endif
gpio_config_t io_conf = {
.mode = GPIO_MODE_INPUT_OUTPUT,
};
@@ -200,12 +208,12 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]")
};
TEST_ESP_OK(dedic_gpio_new_bundle(&bundle_config, &bundle));
// enable interrupt on GPIO1
TEST_ESP_OK(gpio_set_intr_type(1, GPIO_INTR_POSEDGE));
// enable interrupt
TEST_ESP_OK(gpio_set_intr_type(bundle_gpios[1], GPIO_INTR_POSEDGE));
// install gpio isr service
TEST_ESP_OK(gpio_install_isr_service(0));
// hook isr handler for specific gpio pin
TEST_ESP_OK(gpio_isr_handler_add(1, test_dedic_gpio_isr_callback, sem));
TEST_ESP_OK(gpio_isr_handler_add(bundle_gpios[1], test_dedic_gpio_isr_callback, sem));
// trigger a posedge on GPIO1
dedic_gpio_bundle_write(bundle, BIT(1), 0x00);
@@ -214,7 +222,7 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]")
TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(sem, pdMS_TO_TICKS(1000)));
// remove isr handler for gpio number
TEST_ESP_OK(gpio_isr_handler_remove(1));
TEST_ESP_OK(gpio_isr_handler_remove(bundle_gpios[1]));
// uninstall GPIO interrupt service
gpio_uninstall_isr_service();
components/esp_driver_gpio/test_apps/gpio_extensions/pytest_gpio_extensions.py
+1
View File
@@ -28,6 +28,7 @@ def test_gpio_filter(dut: IdfDut) -> None:
@pytest.mark.esp32h2
@pytest.mark.esp32s2
@pytest.mark.esp32s3
@pytest.mark.esp32p4
@pytest.mark.generic
@pytest.mark.parametrize('config', CONFIGS, indirect=True)
def test_dedic_gpio(dut: IdfDut) -> None:
components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h
+57
View File
@@ -0,0 +1,57 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "riscv/csr.h"
/*fast gpio*/
#define CSR_GPIO_OEN_USER 0x803
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
{
// the OEN register is active low
RV_CLEAR_CSR(CSR_GPIO_OEN_USER, mask);
}
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
{
RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
}
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
{
uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
return value;
}
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
{
uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
return value;
}
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
{
RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
}
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/dedic_gpio_periph.c
+58
View File
@@ -0,0 +1,58 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_sig_map.h"
#include "soc/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.irq = -1,
.cores = {
[0] = {
.in_sig_per_channel = {
[0] = CORE_GPIO_IN_PAD_IN0_IDX,
[1] = CORE_GPIO_IN_PAD_IN1_IDX,
[2] = CORE_GPIO_IN_PAD_IN2_IDX,
[3] = CORE_GPIO_IN_PAD_IN3_IDX,
[4] = CORE_GPIO_IN_PAD_IN4_IDX,
[5] = CORE_GPIO_IN_PAD_IN5_IDX,
[6] = CORE_GPIO_IN_PAD_IN6_IDX,
[7] = CORE_GPIO_IN_PAD_IN7_IDX,
},
.out_sig_per_channel = {
[0] = CORE_GPIO_OUT_PAD_OUT0_IDX,
[1] = CORE_GPIO_OUT_PAD_OUT1_IDX,
[2] = CORE_GPIO_OUT_PAD_OUT2_IDX,
[3] = CORE_GPIO_OUT_PAD_OUT3_IDX,
[4] = CORE_GPIO_OUT_PAD_OUT4_IDX,
[5] = CORE_GPIO_OUT_PAD_OUT5_IDX,
[6] = CORE_GPIO_OUT_PAD_OUT6_IDX,
[7] = CORE_GPIO_OUT_PAD_OUT7_IDX,
}
},
[1] = {
.in_sig_per_channel = {
[0] = CORE_GPIO_IN_PAD_IN8_IDX,
[1] = CORE_GPIO_IN_PAD_IN9_IDX,
[2] = CORE_GPIO_IN_PAD_IN10_IDX,
[3] = CORE_GPIO_IN_PAD_IN11_IDX,
[4] = CORE_GPIO_IN_PAD_IN12_IDX,
[5] = CORE_GPIO_IN_PAD_IN13_IDX,
[6] = CORE_GPIO_IN_PAD_IN14_IDX,
[7] = CORE_GPIO_IN_PAD_IN15_IDX,
},
.out_sig_per_channel = {
[0] = CORE_GPIO_OUT_PAD_OUT8_IDX,
[1] = CORE_GPIO_OUT_PAD_OUT9_IDX,
[2] = CORE_GPIO_OUT_PAD_OUT10_IDX,
[3] = CORE_GPIO_OUT_PAD_OUT11_IDX,
[4] = CORE_GPIO_OUT_PAD_OUT12_IDX,
[5] = CORE_GPIO_OUT_PAD_OUT13_IDX,
[6] = CORE_GPIO_OUT_PAD_OUT14_IDX,
[7] = CORE_GPIO_OUT_PAD_OUT15_IDX,
}
},
},
};
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -7,6 +7,10 @@ config SOC_ANA_CMPR_SUPPORTED
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_UART_SUPPORTED
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+1 -1
View File
@@ -19,7 +19,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 //TODO: IDF-6496
#define SOC_ANA_CMPR_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: IDF-7552
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1