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Merge branch 'fix/fix_mpll_enable_order_v6.1' into 'release/v6.1'

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fix(esp_hw_support): fix esp32s31 mpll initialization (v6.1)

See merge request espressif/esp-idf!50430
This commit is contained in:
Jiang Jiang Jian
2026-07-16 11:28:17 +08:00
parent 0196213a13 7c23080017
commit f6eadf3e95
11 changed files with 33 additions and 21 deletions
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8
components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
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@@ -32,6 +32,8 @@
#include "soc/reset_reasons.h"
#include "hal/assist_debug_ll.h"
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/psram_ctrlr_ll.h"
ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31");
@@ -53,6 +55,12 @@ static inline void bootloader_hardware_init(void)
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-14678 Remove this?
regi2c_ctrl_ll_master_configure_clock();
#endif
/* Disable MPLL by default, during mmu_hal_init, a valid clock source is required for the PSRAM,
so before shutting down mpll, the PSRAM clock source should be selected to an always-on source. */
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
clk_ll_mpll_disable();
}
void bootloader_enable_cpu_reset_info(void)