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Merge branch 'fix/fix_parlio_tx_sample_edge_v5.4' into 'release/v5.4'

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change(parlio_tx): use shift edge instead sample edge (v5.4)

See merge request espressif/esp-idf!46937
This commit is contained in:
morris
2026-05-09 15:17:31 +08:00
parent 8aeefe165c 61dcb5b61f
commit f6e3d087a7
10 changed files with 48 additions and 40 deletions
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components/esp_driver_parlio/include/driver/parlio_tx.h
+5 -2
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -33,7 +33,10 @@ typedef struct {
size_t trans_queue_depth; /*!< Depth of internal transaction queue */ size_t trans_queue_depth; /*!< Depth of internal transaction queue */
size_t max_transfer_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */ size_t max_transfer_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */
size_t dma_burst_size; /*!< DMA burst size, in bytes */ size_t dma_burst_size; /*!< DMA burst size, in bytes */
parlio_sample_edge_t sample_edge; /*!< Parallel IO sample edge */ union {
parlio_sample_edge_t sample_edge __attribute__((deprecated("Please use `shift_edge` instead"))); /*!< Parallel IO sample edge */
parlio_shift_edge_t shift_edge; /*!< Parallel IO Tx shift edge */
};
parlio_bit_pack_order_t bit_pack_order; /*!< Set the order of packing the bits into bytes (only works when `data_width` < 8) */ parlio_bit_pack_order_t bit_pack_order; /*!< Set the order of packing the bits into bytes (only works when `data_width` < 8) */
struct { struct {
uint32_t clk_gate_en: 1; /*!< Enable TX clock gating, uint32_t clk_gate_en: 1; /*!< Enable TX clock gating,
components/esp_driver_parlio/src/parlio_tx.c
+3 -3
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -371,8 +371,8 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
if (data_width < 8) { if (data_width < 8) {
parlio_ll_tx_set_bit_pack_order(hal->regs, config->bit_pack_order); parlio_ll_tx_set_bit_pack_order(hal->regs, config->bit_pack_order);
} }
// set sample clock edge
parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge); parlio_ll_tx_set_shift_clock_edge(hal->regs, config->shift_edge);
#if SOC_PARLIO_TX_SIZE_BY_DMA #if SOC_PARLIO_TX_SIZE_BY_DMA
// Always use DATA LEN EOF as the Parlio TX EOF // Always use DATA LEN EOF as the Parlio TX EOF
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c
+1 -1
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@@ -50,7 +50,7 @@ static void test_parlio_sleep_retention(bool allow_pd)
.trans_queue_depth = 8, .trans_queue_depth = 8,
.max_transfer_size = 128, .max_transfer_size = 128,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.allow_pd = allow_pd, .flags.allow_pd = allow_pd,
}; };
TEST_ESP_OK(parlio_new_tx_unit(&tx_config, &tx_unit)); TEST_ESP_OK(parlio_new_tx_unit(&tx_config, &tx_unit));
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
+6 -6
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -96,7 +96,7 @@ TEST_CASE("parallel_tx_unit_trans_done_event", "[parlio_tx]")
.trans_queue_depth = 8, .trans_queue_depth = 8,
.max_transfer_size = 128, .max_transfer_size = 128,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_POS,
}; };
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -148,7 +148,7 @@ TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]")
.trans_queue_depth = 4, .trans_queue_depth = 4,
.max_transfer_size = 256, .max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_POS,
}; };
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -209,7 +209,7 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
.trans_queue_depth = 4, .trans_queue_depth = 4,
.max_transfer_size = 64, .max_transfer_size = 64,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_POS,
}; };
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -261,7 +261,7 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
.trans_queue_depth = 4, .trans_queue_depth = 4,
.max_transfer_size = 64, .max_transfer_size = 64,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO .flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO
}; };
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
@@ -381,7 +381,7 @@ TEST_CASE("parallel tx unit use external non-free running clock", "[parlio_tx]")
.trans_queue_depth = 8, .trans_queue_depth = 8,
.max_transfer_size = 256, .max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_POS,
}; };
uint8_t test_round = 50; uint8_t test_round = 50;
components/hal/esp32c5/include/hal/parlio_ll.h
+6 -7
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -516,16 +516,15 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
} }
/** /**
* @brief Set the sample clock edge * @brief Set the shift clock edge
* *
* @param dev Parallel IO register base address * @param dev Parallel IO register base address
* @param edge Sample clock edge * @param edge Shift clock edge
*/ */
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{ {
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_i_inv = invert; dev->tx_clk_cfg.tx_clk_o_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
} }
/** /**
components/hal/esp32c6/include/hal/parlio_ll.h
+4 -4
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -492,12 +492,12 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
} }
/** /**
* @brief Set the sample clock edge * @brief Set the shift clock edge
* *
* @param dev Parallel IO register base address * @param dev Parallel IO register base address
* @param edge Sample clock edge * @param edge Shift clock edge
*/ */
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{ {
dev->tx_cfg0.tx_smp_edge_sel = edge; dev->tx_cfg0.tx_smp_edge_sel = edge;
} }
components/hal/esp32h2/include/hal/parlio_ll.h
+6 -7
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -500,16 +500,15 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
} }
/** /**
* @brief Set the sample clock edge * @brief Set the shift clock edge
* *
* @param dev Parallel IO register base address * @param dev Parallel IO register base address
* @param edge Sample clock edge * @param edge Shift clock edge
*/ */
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{ {
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_i_inv = invert; dev->tx_clk_cfg.tx_clk_o_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
} }
/** /**
components/hal/esp32p4/include/hal/parlio_ll.h
+6 -7
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -565,16 +565,15 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
} }
/** /**
* @brief Set the sample clock edge * @brief Set the shift clock edge
* *
* @param dev Parallel IO register base address * @param dev Parallel IO register base address
* @param edge Sample clock edge * @param edge Shift clock edge
*/ */
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{ {
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_i_inv = invert; dev->tx_clk_cfg.tx_clk_o_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
} }
/** /**
components/hal/include/hal/parlio_types.h
+10 -2
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -16,13 +16,21 @@ extern "C" {
#endif #endif
/** /**
* @brief Parallel IO sample edge * @brief Parallel IO Rx sample edge
*/ */
typedef enum { typedef enum {
PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */ PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */
PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */ PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */
} parlio_sample_edge_t; } parlio_sample_edge_t;
/**
* @brief Parallel IO Tx shift edge
*/
typedef enum {
PARLIO_SHIFT_EDGE_POS, /*!< Shift data on rising edge of clock */
PARLIO_SHIFT_EDGE_NEG, /*!< Shift data on falling edge of clock */
} parlio_shift_edge_t;
/** /**
* @brief Parallel IO bit packing order * @brief Parallel IO bit packing order
* *
examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c
+1 -1
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@@ -145,7 +145,7 @@ void app_main(void)
.output_clk_freq_hz = EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ, .output_clk_freq_hz = EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ,
.trans_queue_depth = 32, .trans_queue_depth = 32,
.max_transfer_size = EXAMPLE_LED_MATRIX_H_RES * sizeof(lv_color_t) * 2, // 2 lines as the maximum transfer size .max_transfer_size = EXAMPLE_LED_MATRIX_H_RES * sizeof(lv_color_t) * 2, // 2 lines as the maximum transfer size
.sample_edge = PARLIO_SAMPLE_EDGE_POS, .shift_edge = PARLIO_SHIFT_EDGE_NEG,
}; };
ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit)); ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit));
ESP_ERROR_CHECK(parlio_tx_unit_enable(tx_unit)); ESP_ERROR_CHECK(parlio_tx_unit_enable(tx_unit));