Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-03 03:31:41 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(wifi): fix regdma restore ba bitmap fail issue

Browse Source
This commit is contained in:
muhaidong
2026-09-15 20:51:25 +08:00
parent 81014a4da3
commit f5cf14b319
4 changed files with 74 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c
+3 -2
View File
@@ -74,7 +74,7 @@ esp_err_t sleep_clock_modem_retention_init(void *arg)
#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
#define N_REGS_LPCON() (((MODEM_LPCON_MODEM_INTR_STATUS_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1)
const static sleep_retention_entries_config_t modem_regs_retention[] = {
/* !!! pll_source_regs_retention link above does not above guarantee that the PMU has released the clock gate for the PLL.
/* !!! pll_source_regs_retention link above does not guarantee that the PMU has released the clock gate for the PLL.
* And due to hardware limitations, REGDMA is also unable to obtain the PMU's PLL gate status when the chip is in PD_TOP mode.
* So WORKAROUND with issue a dummy write to MODEM_SYSCON_DATE_REG as the first REGDMA node to avoid an APB access timeout
* during the subsequent REGDMA operations. */
@@ -82,7 +82,8 @@ esp_err_t sleep_clock_modem_retention_init(void *arg)
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(0), HP_SYS_CLKRST_REF_160M_CTRL0_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN, HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M, 1, 0), .owner = ENTRY(1)},
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(1), HP_SYS_CLKRST_MODEM_CONF_REG, 0x3d, 0x3d, 1, 0), .owner = ENTRY(1)},
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(1), HP_SYS_CLKRST_MODEM_CONF_REG, 0x15, 0xff, 1, 0), .owner = ENTRY(1)},
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(2), HP_SYS_CLKRST_MODEM_CONF_REG, 0x1d, 0xff, 1, 0), .owner = ENTRY(1)},
};
esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
components/esp_hw_support/port/esp32s31/pmu_sleep.c
+20 -4
View File
@@ -14,10 +14,10 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/pmu_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "esp_private/esp_pmu.h"
#include "esp_private/esp_clk_tree_common.h"
#include "pmu_param.h"
#include "hal/clk_gate_ll.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/lp_aon_hal.h"
@@ -406,9 +406,25 @@ bool pmu_sleep_finish(bool dslp)
esp_psram_impl_exit_halfsleep_mode();
#endif
#endif
/* PLL_SOURCE retention may leave BBPLL powered on; align HW to clk_tree ref. */
if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL) && !HP_SYS_CLKRST.modem_conf.modem_pll_clk_en) {
clk_ll_bbpll_disable();
const bool modem_pll_clk_enabled = clk_gate_ll_modem_pll_clk_is_enabled();
assert(modem_pll_clk_enabled == clk_gate_ll_modem_clk_source_is_pll());
if (!modem_pll_clk_enabled) { // wake up from non-modem clock retention
/* Workaround for issue WIFI-7620
* The BA bitmap and start sequence number are updated in the read-only
* registers only after the PLL clock is available. */
bool ref_160_enabled = clk_gate_ll_ref_160m_clk_is_enabled();
if (!ref_160_enabled) {
_clk_gate_ll_ref_160m_clk_en(true);
}
_clk_gate_ll_modem_pll_source_cg_en(true);
_clk_gate_ll_modem_pll_source_cg_en(false);
if (!ref_160_enabled) {
_clk_gate_ll_ref_160m_clk_en(false);
}
if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL)) { // clear align HW to clk_tree ref
clk_ll_bbpll_disable();
}
}
}