fix(gdma): treat burst size 0 and 1 as burst disabled

The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.

GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.

The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:

- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)

Callers that really want no burst can now set `dma_burst_size` to 1.

docs/en/api-reference/peripherals/async_crc.rst

@@ -101,7 +101,7 @@ When creating a driver instance, you need to configure:
 
 - **backlog**: Maximum number of pending CRC requests that can be queued. Higher values use more memory but provide better throughput for bursty workloads.
 - **intr_priority**: DMA interrupt priority. Set to ``0`` to use the default low/medium priority, or set a non-zero value to request a specific interrupt priority.
-- **dma_burst_size**: DMA transfer burst size in bytes.
+- **dma_burst_size**: DMA transfer burst size in bytes. Set to ``0`` to use the driver default (16 bytes), or to ``1`` to disable the data burst.
 
 The driver handle ``crc_hdl`` is an opaque pointer that you use for all subsequent operations.
 
@@ -327,6 +327,7 @@ The ``dma_burst_size`` affects DMA transfer efficiency:
 
 - Larger burst sizes can improve throughput
 - Typical values: 16, 32, 64 bytes
+- Set to ``0`` to use the driver default (16 bytes), or to ``1`` to disable the data burst
 
 The optimal value depends on your chip's DMA controller capabilities.