Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-09-22 13:01:16 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(gdma): treat burst size 0 and 1 as burst disabled

Browse Source 
The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.

GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.

The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:

- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)

Callers that really want no burst can now set `dma_burst_size` to 1.
This commit is contained in:
morris
2026-08-31 13:07:36 +08:00
parent c17ec317ef
commit f5afb99e3b
35 changed files with 203 additions and 111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
docs/en/api-reference/peripherals/async_crc.rst
View File

@@ -101,7 +101,7 @@ When creating a driver instance, you need to configure:
- **backlog**: Maximum number of pending CRC requests that can be queued. Higher values use more memory but provide better throughput for bursty workloads.
- **intr_priority**: DMA interrupt priority. Set to ``0`` to use the default low/medium priority, or set a non-zero value to request a specific interrupt priority.
- **dma_burst_size**: DMA transfer burst size in bytes.
- **dma_burst_size**: DMA transfer burst size in bytes. Set to ``0`` to use the driver default (16 bytes), or to ``1`` to disable the data burst.
The driver handle ``crc_hdl`` is an opaque pointer that you use for all subsequent operations.
@@ -327,6 +327,7 @@ The ``dma_burst_size`` affects DMA transfer efficiency:
- Larger burst sizes can improve throughput
- Typical values: 16, 32, 64 bytes
- Set to ``0`` to use the driver default (16 bytes), or to ``1`` to disable the data burst
The optimal value depends on your chip's DMA controller capabilities.

6
docs/en/api-reference/peripherals/async_memcpy.rst
View File

@@ -92,7 +92,11 @@ Select a DMA backend explicitly when installing the driver. The AHB GDMA backend
:SOC_LP_AHB_GDMA_SUPPORTED: - :cpp:func:`esp_async_memcpy_install_gdma_lp_ahb`
:SOC_DW_GDMA_SUPPORTED: - :cpp:func:`esp_async_memcpy_install_dw_gdma`
For a single blocking copy, set :cpp:member:`async_memcpy_config_t::backlog` to 1. Increase it when multiple copies can be pending. :cpp:member:`async_memcpy_config_t::dma_burst_size` controls the burst size in bytes; start with 16 and tune it only after measuring your workload. Set :cpp:member:`async_memcpy_config_t::weight` to 0 unless weighted arbitration is supported and your application needs to adjust its average bus bandwidth.
For a single blocking copy, set :cpp:member:`async_memcpy_config_t::backlog` to 1. Increase it when multiple copies can be pending.
:cpp:member:`async_memcpy_config_t::dma_burst_size` controls the burst size in bytes; start with 16 and tune it only after measuring your workload. Set it to ``0`` to use the driver default (16 bytes), or to ``1`` to disable the data burst.
Set :cpp:member:`async_memcpy_config_t::weight` to 0 unless weighted arbitration is supported and your application needs to adjust its average bus bandwidth.
Scenario 2: Continue Working While DMA Copies
==============================================