fix(gdma): treat burst size 0 and 1 as burst disabled

The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.

GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.

The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:

- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)

Callers that really want no burst can now set `dma_burst_size` to 1.

components/esp_driver_uart/src/uhci.c

@@ -204,7 +204,7 @@ static esp_err_t uhci_gdma_initialize(uhci_controller_handle_t uhci_ctrl, const
 
     gdma_transfer_config_t transfer_cfg = {
         .access_ext_mem = true,
-        .max_data_burst_size = config->dma_burst_size,
+        .max_data_burst_size = config->dma_burst_size ? config->dma_burst_size : UHCI_DEFAULT_DMA_BURST_SIZE,
     };
     ESP_RETURN_ON_ERROR(gdma_config_transfer(uhci_ctrl->tx_dir.dma_chan, &transfer_cfg), TAG, "Config DMA tx channel transfer failed");
 

components/esp_driver_uart/src/uhci_private.h

@@ -23,6 +23,7 @@ extern "C" {
 typedef struct uhci_controller_t uhci_controller_t;
 
 #define UHCI_PM_LOCK_NAME_LEN_MAX              16
+#define UHCI_DEFAULT_DMA_BURST_SIZE            16  // Default DMA burst size in bytes, used when user config leaves dma_burst_size as 0
 
 #if CONFIG_UHCI_ISR_HANDLER_IN_IRAM
 #define UHCI_MEM_ALLOC_CAPS     (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)