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fix(gdma): treat burst size 0 and 1 as burst disabled
The GDMA layer used `max_data_burst_size == 0` as the only way to disable the data burst. That conflicts with the upstream drivers' convention where a zeroed config struct means "unset", so users had no way to ask for the driver default burst size. GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no benefit over the non-burst mode. The MSPI alignment constraint under Flash Encryption / PSRAM ECC still takes precedence and is reported with a warning. The upstream drivers using GDMA now apply their own default burst size (16 bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver: - esp_async_crc (AHB / AXI GDMA backend) - esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend) Callers that really want no burst can now set `dma_burst_size` to 1.
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@@ -22,7 +22,7 @@ typedef struct {
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size_t max_transmit_size; /*!< Maximum transfer size in one transaction, in bytes. Note that this is the total size of all buffers combined */
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size_t max_transmit_buffer_count; /*!< Maximum number of buffers that can be transmitted together in one transaction, via `uhci_multi_buffer_transmit()`. Set to 0 or 1 if only single-buffer transmit (`uhci_transmit()`) is needed. */
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size_t max_receive_internal_mem; /*!< Expected maximum buffer size for uhci_receive(). This value determines the number of descriptors in the receive DMA chain. Each DMA descriptor can reference a buffer of up to X bytes (depending on the chip). For large transfers, at least two descriptors are recommended for ping-pong operation. */
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size_t dma_burst_size; /*!< DMA burst size, in bytes. Set to 0 to disable data burst. Otherwise, use a power of 2. */
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size_t dma_burst_size; /*!< DMA burst size, in bytes, must be a power of 2. Set to 0 to use the driver default. Set to 1 to disable the data burst. */
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size_t max_packet_receive; /*!< Max receive size, auto stop receiving after reach this value, only valid when `length_eof` set true */
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struct {
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