fix(gdma): treat burst size 0 and 1 as burst disabled

The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.

GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.

The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:

- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)

Callers that really want no burst can now set `dma_burst_size` to 1.

components/esp_driver_i2s/include/driver/i2s_common.h

@@ -74,7 +74,7 @@ typedef struct {
     uint32_t            dma_frame_num;      /*!< I2S frame number in one DMA buffer. One frame means one-time sample data in all slots,
                                              *   it should be the multiple of `3` when the data bit width is 24.
                                              */
-    size_t              dma_burst_size;     /*!< DMA data burst size in bytes. Set to 0 to use driver default (32).
+    size_t              dma_burst_size;     /*!< DMA data burst size in bytes. Set to 0 to use the driver default.
                                              *   When non-zero, must be a chip-supported power of 2 (see GDMA driver or chip TRM).
                                              *   Ignored on chips that do not support configurable burst size.
                                              */