mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
fix(gdma): treat burst size 0 and 1 as burst disabled
The GDMA layer used `max_data_burst_size == 0` as the only way to disable the data burst. That conflicts with the upstream drivers' convention where a zeroed config struct means "unset", so users had no way to ask for the driver default burst size. GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no benefit over the non-burst mode. The MSPI alignment constraint under Flash Encryption / PSRAM ECC still takes precedence and is reported with a warning. The upstream drivers using GDMA now apply their own default burst size (16 bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver: - esp_async_crc (AHB / AXI GDMA backend) - esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend) Callers that really want no burst can now set `dma_burst_size` to 1.
This commit is contained in:
morris
@@ -162,25 +162,20 @@ static void test_memory_copy_blocking(async_memcpy_handle_t driver)
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.align = 16,
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};
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for (int i = 0; i < sizeof(test_buffer_size) / sizeof(test_buffer_size[0]); i++) {
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// Test different align edge
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for (int off = 0; off < 4; off++) {
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test_context.buffer_size = test_buffer_size[i];
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test_context.seed = i;
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if (!gdma_test_mspi_strict_alignment_required()) {
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test_context.src_offset = off;
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test_context.dst_offset = off;
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}
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async_memcpy_setup_testbench(&test_context);
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test_context.buffer_size = test_buffer_size[i];
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test_context.seed = i;
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async_memcpy_setup_testbench(&test_context);
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TEST_ESP_OK(esp_memcpy_blocking(driver, test_context.to_addr, test_context.from_addr, test_context.copy_size, -1));
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async_memcpy_verify_and_clear_testbench(test_context.copy_size, test_context.src_buf, test_context.dst_buf,
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test_context.from_addr, test_context.to_addr);
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}
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TEST_ESP_OK(esp_memcpy_blocking(driver, test_context.to_addr, test_context.from_addr, test_context.copy_size, -1));
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async_memcpy_verify_and_clear_testbench(test_context.copy_size, test_context.src_buf, test_context.dst_buf,
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test_context.from_addr, test_context.to_addr);
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}
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}
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TEST_CASE("memory copy by DMA (blocking)", "[async mcp]")
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{
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// Aligned copies with the driver default burst.
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// Unaligned dest is covered by "memory copy with dest address unaligned" case.
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async_memcpy_config_t config = {
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.backlog = 1,
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.dma_burst_size = 0,
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@@ -247,63 +242,83 @@ TEST_CASE("memory copy by DMA (blocking)", "[async mcp]")
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}
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}
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TEST_CASE("memory copy with dest address unaligned", "[async mcp]")
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typedef esp_err_t (*test_mcp_install_fn)(const async_memcpy_config_t *config, async_memcpy_handle_t *mcp);
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// SRAM can disable burst to cover the unaligned software path on chips whose RX
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// burst requires dest alignment. PSRAM cannot: the external-memory block size
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// (e.g. ESP32-S3 ext_mem_bk_size) is programmed together with the burst size and
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// must match the cache line. Dest is cache-split so the DMA body stays aligned.
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[[maybe_unused]] static void test_unaligned_dest_with_backend(const char *name, test_mcp_install_fn install, bool psram_capable)
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{
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[[maybe_unused]] async_memcpy_config_t driver_config = {
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async_memcpy_config_t config = {
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.backlog = 4,
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.dma_burst_size = 32,
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};
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[[maybe_unused]] async_memcpy_handle_t driver = NULL;
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async_memcpy_handle_t driver = NULL;
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#if SOC_GDMA_SUPPORTED && (GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT || CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION)
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config.dma_burst_size = 1;
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#endif
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printf("Testing memcpy by %s\r\n", name);
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TEST_ESP_OK(install(&config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, false, false);
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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#if SOC_HAS(SPIRAM)
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if (psram_capable) {
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config.dma_burst_size = 32;
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#if CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
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// Weighted arbitration still needs every buffer aligned to the burst
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// size, including the TX source body. Keep burst disabled there.
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config.dma_burst_size = 1;
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#endif
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printf("Testing memcpy by %s (PSRAM)\r\n", name);
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TEST_ESP_OK(install(&config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, true, true);
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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}
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#else
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(void)psram_capable;
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#endif // SOC_HAS(SPIRAM)
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}
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TEST_CASE("memory copy with dest address unaligned", "[async mcp]")
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{
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if (gdma_test_mspi_strict_alignment_required()) {
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TEST_PASS_MESSAGE("MSPI strict alignment required (Flash Encryption / PSRAM ECC), skip this test");
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}
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#if SOC_CP_DMA_SUPPORTED
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printf("Testing memcpy by CP DMA\r\n");
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TEST_ESP_OK(esp_async_memcpy_install_cpdma(&driver_config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, false, false);
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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test_unaligned_dest_with_backend("CP DMA", esp_async_memcpy_install_cpdma, false);
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#endif // SOC_CP_DMA_SUPPORTED
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#if SOC_HAS(AHB_GDMA) && !GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
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printf("Testing memcpy by AHB GDMA\r\n");
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TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, false, false);
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#if GDMA_LL_GET(AHB_PSRAM_CAPABLE) && SOC_HAS(SPIRAM)
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test_memcpy_with_dest_addr_unaligned(driver, true, true);
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#endif // GDMA_LL_GET(AHB_PSRAM_CAPABLE) && SOC_HAS(SPIRAM)
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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#if SOC_HAS(AHB_GDMA)
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#if GDMA_LL_GET(AHB_PSRAM_CAPABLE)
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test_unaligned_dest_with_backend("AHB GDMA", esp_async_memcpy_install_gdma_ahb, true);
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#else
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test_unaligned_dest_with_backend("AHB GDMA", esp_async_memcpy_install_gdma_ahb, false);
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#endif
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#endif // SOC_HAS(AHB_GDMA)
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#if SOC_HAS(AXI_GDMA) && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
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printf("Testing memcpy by AXI GDMA\r\n");
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TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, false, false);
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#if GDMA_LL_GET(AXI_PSRAM_CAPABLE) && SOC_HAS(SPIRAM)
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test_memcpy_with_dest_addr_unaligned(driver, true, true);
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#endif // GDMA_LL_GET(AXI_PSRAM_CAPABLE) && SOC_HAS(SPIRAM)
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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#if SOC_HAS(AXI_GDMA)
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#if GDMA_LL_GET(AXI_PSRAM_CAPABLE)
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test_unaligned_dest_with_backend("AXI GDMA", esp_async_memcpy_install_gdma_axi, true);
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#else
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test_unaligned_dest_with_backend("AXI GDMA", esp_async_memcpy_install_gdma_axi, false);
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#endif
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#endif // SOC_HAS(AXI_GDMA)
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#if SOC_HAS(LP_AHB_GDMA) && !CONFIG_GDMA_ENABLE_WEIGHTED_ARBITRATION
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printf("Testing memcpy by LP AHB GDMA\r\n");
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TEST_ESP_OK(esp_async_memcpy_install_gdma_lp_ahb(&driver_config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, false, false);
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#if GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE) && SOC_HAS(SPIRAM)
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test_memcpy_with_dest_addr_unaligned(driver, true, true);
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#endif // GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE) && SOC_HAS(SPIRAM)
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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#if SOC_HAS(LP_AHB_GDMA)
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#if GDMA_LL_GET(LP_AHB_PSRAM_CAPABLE)
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test_unaligned_dest_with_backend("LP AHB GDMA", esp_async_memcpy_install_gdma_lp_ahb, true);
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#else
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test_unaligned_dest_with_backend("LP AHB GDMA", esp_async_memcpy_install_gdma_lp_ahb, false);
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#endif
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#endif // SOC_HAS(LP_AHB_GDMA)
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#if SOC_HAS(DW_GDMA)
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printf("Testing memcpy by DW_GDMA\r\n");
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TEST_ESP_OK(esp_async_memcpy_install_dw_gdma(&driver_config, &driver));
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test_memcpy_with_dest_addr_unaligned(driver, false, false);
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#if SOC_HAS(SPIRAM)
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test_memcpy_with_dest_addr_unaligned(driver, true, true);
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#endif // SOC_HAS(SPIRAM)
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TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
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test_unaligned_dest_with_backend("DW_GDMA", esp_async_memcpy_install_dw_gdma, true);
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#endif // SOC_HAS(DW_GDMA)
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}
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@@ -941,6 +941,13 @@ static void test_gdma_burst_size_validation(gdma_new_channel_func_t new_channel,
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};
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TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_config));
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// 0 and 1 both mean "disable data burst", and must be accepted even on chips
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// whose hardware burst size is not programmable to 1 (e.g. S3: 16/32/64 only).
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transfer_config.max_data_burst_size = 0;
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TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_config));
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transfer_config.max_data_burst_size = 1;
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TEST_ESP_OK(gdma_config_transfer(tx_chan, &transfer_config));
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transfer_config.max_data_burst_size = 3;
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TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gdma_config_transfer(tx_chan, &transfer_config));
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@@ -13,20 +13,22 @@ def get_flash_encryption_marks(target: str) -> tuple[pytest.MarkDecorator, ...]:
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return (pytest.mark.flash_encryption,)
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@pytest.mark.generic
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def get_psram_marks(target: str) -> tuple[pytest.MarkDecorator, ...]:
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if target == 'esp32s3':
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return (pytest.mark.octal_psram,)
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return (pytest.mark.generic,)
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@pytest.mark.parametrize(
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'config',
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'config, target',
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[
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'release',
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pytest.param('release', target, marks=get_psram_marks(target))
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for target in soc_filtered_targets('SOC_GDMA_SUPPORTED == 1 or SOC_CP_DMA_SUPPORTED == 1')
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],
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indirect=True,
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)
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@idf_parametrize(
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'target',
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['esp32s2', 'esp32s31', 'esp32c2', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32h4', 'esp32p4'],
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indirect=['target'],
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)
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def test_dma(dut: Dut) -> None:
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def test_gdma(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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@@ -40,20 +42,7 @@ def test_dma(dut: Dut) -> None:
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indirect=True,
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)
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@idf_parametrize('target', ['esp32p4'], indirect=['target'])
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def test_dma_esp32p4_rev1(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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@pytest.mark.octal_psram
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@pytest.mark.parametrize(
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'config',
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[
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'release',
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],
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indirect=True,
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)
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@idf_parametrize('target', ['esp32s3'], indirect=['target'])
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def test_dma_psram(dut: Dut) -> None:
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def test_gdma_esp32p4_rev1(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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@@ -66,7 +55,7 @@ def test_dma_psram(dut: Dut) -> None:
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indirect=True,
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)
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@idf_parametrize('target', soc_filtered_targets('SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION == 1'), indirect=['target'])
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def test_dma_weighted_arbitration(dut: Dut) -> None:
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def test_gdma_weighted_arbitration(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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@@ -80,5 +69,5 @@ def test_dma_weighted_arbitration(dut: Dut) -> None:
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],
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indirect=True,
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)
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def test_dma_flash_encryption(dut: Dut) -> None:
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def test_gdma_flash_encryption(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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