fix(gdma): treat burst size 0 and 1 as burst disabled

The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.

GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.

The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:

- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)

Callers that really want no burst can now set `dma_burst_size` to 1.

components/bt/common/ble_log/src/prph/ble_log_prph_uart_dma.c

@@ -27,7 +27,7 @@
 /* ponytail: data burst disabled — UHCI enforces burst-size alignment (addr+len) on
  * uhci_transmit() once GDMA weighted arbitration is enabled, and UART log bandwidth
  * is baud-rate limited anyway, so burst buys nothing here */
-#define BLE_LOG_UART_DMA_BURST_SIZE         (0)
+#define BLE_LOG_UART_DMA_BURST_SIZE         (1)
 #if BLE_LOG_PRPH_UART_DMA_REDIR
 #define BLE_LOG_UART_REDIR_BUF_SIZE         (512)
 #define BLE_LOG_UART_REDIR_FLUSH_PERIOD_US  (1000 * 1000)

components/bt/porting/transport/driver/uart/hci_driver_uart_dma.c

@@ -272,7 +272,7 @@ hci_driver_uart_dma_uhci_install(void)
         .max_transmit_size = HCI_TX_MAX_SIZE,         /* Total bytes of all segments in one transaction. */
         .max_transmit_buffer_count = HCI_TX_MAX_SEGMENT_COUNT, /* Caps uhci_multi_buffer_transmit() array_size. */
         .max_receive_internal_mem = HCI_UHCI_RX_DESC_MEM,      /* Sizes the RX DMA descriptor chain, not the ring. */
-        .dma_burst_size = 32,                         /* Power-of-two burst; 0 would disable burst. */
+        .dma_burst_size = 32,                         /* Power-of-two burst size in bytes. */
         .rx_eof_flags.idle_eof = 1,                   /* Frame ends when the UART RX line goes idle. */
     };
     uhci_event_callbacks_t uhci_cbs = {

components/bt/porting_btdm/transport/driver/uart/hci_driver_uart_dma.c

@@ -279,7 +279,7 @@ hci_driver_uart_dma_uhci_install(void)
         .max_transmit_size = HCI_TX_MAX_SIZE,         /* Total bytes of all segments in one transaction. */
         .max_transmit_buffer_count = HCI_TX_MAX_SEGMENT_COUNT, /* Caps uhci_multi_buffer_transmit() array_size. */
         .max_receive_internal_mem = HCI_UHCI_RX_DESC_MEM,      /* Sizes the RX DMA descriptor chain, not the ring. */
-        .dma_burst_size = 32,                         /* Power-of-two burst; 0 would disable burst. */
+        .dma_burst_size = 32,                         /* Power-of-two burst size in bytes. */
         .rx_eof_flags.idle_eof = 1,                   /* Frame ends when the UART RX line goes idle. */
     };
     uhci_event_callbacks_t uhci_cbs = {