driver: add parallel IO TX driver

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -39,6 +39,10 @@ config SOC_ETM_SUPPORTED
     bool
     default y
 
+config SOC_PARLIO_SUPPORTED
+    bool
+    default y
+
 config SOC_BT_SUPPORTED
     bool
     default y
@@ -667,6 +671,30 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
     bool
     default y
 
+config SOC_PARLIO_GROUPS
+    int
+    default 1
+
+config SOC_PARLIO_TX_UNITS_PER_GROUP
+    int
+    default 1
+
+config SOC_PARLIO_RX_UNITS_PER_GROUP
+    int
+    default 1
+
+config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
+    int
+    default 16
+
+config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
+    int
+    default 16
+
+config SOC_PARLIO_TX_RX_SHARE_INTERRUPT
+    bool
+    default y
+
 config SOC_RSA_MAX_BIT_LEN
     int
     default 3072

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -405,6 +405,22 @@ typedef enum {
     LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
 } soc_periph_ledc_clk_src_legacy_t;
 
+//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of PARLIO
+ */
+#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
+
+/**
+ * @brief PARLIO clock source
+ */
+typedef enum {
+    PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+    PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
+    PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M,   /*!< Select PLL_F240M as the default clock choice */
+} soc_periph_parlio_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c6/include/soc/periph_defs.h

@@ -37,6 +37,7 @@ typedef enum {
     PERIPH_GDMA_MODULE,
     PERIPH_MCPWM0_MODULE,
     PERIPH_ETM_MODULE,
+    PERIPH_PARLIO_MODULE,
     PERIPH_SYSTIMER_MODULE,
     PERIPH_SARADC_MODULE,
     PERIPH_TEMPSENSOR_MODULE,

components/soc/esp32c6/include/soc/soc_caps.h

@@ -34,6 +34,7 @@
 #define SOC_MCPWM_SUPPORTED             1
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_ETM_SUPPORTED               1
+#define SOC_PARLIO_SUPPORTED            1
 #define SOC_BT_SUPPORTED                1
 #define SOC_IEEE802154_SUPPORTED        1
 #define SOC_ASYNC_MEMCPY_SUPPORTED      1
@@ -279,6 +280,14 @@
 /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
 // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
 
+/*-------------------------- PARLIO CAPS --------------------------------------*/
+#define SOC_PARLIO_GROUPS                    1U  /*!< Number of parallel IO peripherals */
+#define SOC_PARLIO_TX_UNITS_PER_GROUP        1U  /*!< number of TX units in each group */
+#define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
+#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
+#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
+#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
+
 /*--------------------------- RSA CAPS ---------------------------------------*/
 #define SOC_RSA_MAX_BIT_LEN    (3072)
 

components/soc/esp32c6/parlio_periph.c

@@ -0,0 +1,66 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/parlio_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const parlio_signal_conn_t parlio_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_PARLIO_MODULE,
+            .tx_irq_id = ETS_PARL_IO_INTR_SOURCE,
+            .rx_irq_id = ETS_PARL_IO_INTR_SOURCE,
+            .tx_units = {
+                [0] = {
+                    .data_sigs = {
+                        PARL_TX_DATA0_IDX,
+                        PARL_TX_DATA1_IDX,
+                        PARL_TX_DATA2_IDX,
+                        PARL_TX_DATA3_IDX,
+                        PARL_TX_DATA4_IDX,
+                        PARL_TX_DATA5_IDX,
+                        PARL_TX_DATA6_IDX,
+                        PARL_TX_DATA7_IDX,
+                        PARL_TX_DATA8_IDX,
+                        PARL_TX_DATA9_IDX,
+                        PARL_TX_DATA10_IDX,
+                        PARL_TX_DATA11_IDX,
+                        PARL_TX_DATA12_IDX,
+                        PARL_TX_DATA13_IDX,
+                        PARL_TX_DATA14_IDX,
+                        PARL_TX_DATA15_IDX,
+                    },
+                    .clk_out_sig = PARL_TX_CLK_OUT_IDX,
+                    .clk_in_sig = PARL_TX_CLK_IN_IDX,
+                }
+            },
+            .rx_units = {
+                [0] = {
+                    .data_sigs = {
+                        PARL_RX_DATA0_IDX,
+                        PARL_RX_DATA1_IDX,
+                        PARL_RX_DATA2_IDX,
+                        PARL_RX_DATA3_IDX,
+                        PARL_RX_DATA4_IDX,
+                        PARL_RX_DATA5_IDX,
+                        PARL_RX_DATA6_IDX,
+                        PARL_RX_DATA7_IDX,
+                        PARL_RX_DATA8_IDX,
+                        PARL_RX_DATA9_IDX,
+                        PARL_RX_DATA10_IDX,
+                        PARL_RX_DATA11_IDX,
+                        PARL_RX_DATA12_IDX,
+                        PARL_RX_DATA13_IDX,
+                        PARL_RX_DATA14_IDX,
+                        PARL_RX_DATA15_IDX,
+                    },
+                    .clk_out_sig = -1,
+                    .clk_in_sig = PARL_RX_CLK_IN_IDX,
+                }
+            }
+        },
+    },
+};