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fix(esp_hal_usb): Fix internal PHY default settings

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peter.marcisovsky
2026-05-22 09:47:14 +02:00
parent 8f3d8b41c3
commit f4410ccfee
5 changed files with 62 additions and 5 deletions
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components/esp_hal_usb/esp32s3/include/hal/usb_wrap_ll.h
+15 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -209,6 +209,20 @@ FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw,
hw->test_conf.val = test_conf.val;
}
/**
* @brief Route internal FSLS PHY AHB/PHY clock gating to DWC2
*
* Clears clock force-on bits so DWC2 can gate the internal PHY clocks during
* port suspend and internal clock gating.
*
* @param hw Start address of the USB Wrap registers
*/
FORCE_INLINE_ATTR void usb_wrap_ll_enable_automatic_phy_control(usb_wrap_dev_t *hw)
{
hw->otg_conf.ahb_clk_force_on = 0;
hw->otg_conf.phy_clk_force_on = 0;
}
/* ----------------------------- RCC Functions ----------------------------- */
/**