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Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0'

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fix(spi_flash): Add CPU frequency switching during flash encrypted write (v6.0)

See merge request espressif/esp-idf!44304
This commit is contained in:
Jiang Jiang Jian
2025-12-21 15:28:33 +08:00
parent 8c379b517f 469953bd04
commit f409428bf3
49 changed files with 2110 additions and 95 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
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@@ -1083,6 +1083,10 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED
bool
default y
config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1
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@@ -443,6 +443,7 @@
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1)
#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1