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Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0'

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fix(spi_flash): Add CPU frequency switching during flash encrypted write (v6.0)

See merge request espressif/esp-idf!44304
This commit is contained in:
Jiang Jiang Jian
2025-12-21 15:28:33 +08:00
parent 8c379b517f 469953bd04
commit f409428bf3
49 changed files with 2110 additions and 95 deletions
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components/esp_system/port/soc/esp32c5/Kconfig.cpu
+8 -7
View File
@@ -1,12 +1,9 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_160 if SECURE_FLASH_ENC_ENABLED
default ESP_DEFAULT_CPU_FREQ_MHZ_240
help
CPU frequency to be set on application startup. For flash encryption enabled case,
the default CPU frequency is 160MHz as the encrypted flash writes are not stable at
higher CPU clock. Please see SoC Errata document for details.
CPU frequency to be set on application startup.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
@@ -16,10 +13,14 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_240
# Encrypted flash writes aren't supported at 240 MHz.
# Please see SoC Errata document for details.
depends on !SECURE_FLASH_ENC_ENABLED
bool "240 MHz"
help
When 240MHz is selected, esp_flash_write_encrypted() will automatically limit CPU frequency during
execution:
- v1.2 and above chips: limited to 160MHz
- v1.0 and below chips: limited to 80MHz
When 160MHz or lower is selected, no frequency limiting occurs during encrypted writes. Please refer to
the ESP32-C5 SoC Errata document for more details.
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ