feat(sdmmc): add esp32s31 support

Enable SDMMC host support on ESP32-S31 across HAL, SOC caps, tests, examples, and documentation.

components/soc/esp32s31/include/soc/Kconfig.soc_caps.in

@@ -243,6 +243,10 @@ config SOC_PSRAM_DMA_CAPABLE
     bool
     default y
 
+config SOC_SDMMC_HOST_SUPPORTED
+    bool
+    default y
+
 config SOC_CLK_TREE_SUPPORTED
     bool
     default y
@@ -275,6 +279,10 @@ config SOC_TOUCH_SENSOR_SUPPORTED
     bool
     default y
 
+config SOC_GP_LDO_SUPPORTED
+    bool
+    default y
+
 config SOC_RNG_SUPPORTED
     bool
     default y
@@ -783,6 +791,34 @@ config SOC_MMU_PER_EXT_MEM_TARGET
     bool
     default y
 
+config SOC_SDMMC_USE_IOMUX
+    bool
+    default y
+
+config SOC_SDMMC_NUM_SLOTS
+    int
+    default 2
+
+config SOC_SDMMC_DATA_WIDTH_MAX
+    int
+    default 4
+
+config SOC_SDMMC_DELAY_PHASE_NUM
+    int
+    default 8
+
+config SOC_SDMMC_IO_UHS_POWER_EXTERNAL
+    bool
+    default y
+
+config SOC_SDMMC_PSRAM_DMA_CAPABLE
+    bool
+    default y
+
+config SOC_SDMMC_UHS_I_SUPPORTED
+    bool
+    default y
+
 config SOC_SPI_PERIPH_NUM
     int
     default 3

components/soc/esp32s31/include/soc/clk_tree_defs.h

@@ -340,6 +340,21 @@ typedef enum {
     LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST,                 /*!< LP_I2C source clock default choice is RTC_FAST */
 } soc_periph_lp_i2c_clk_src_t;
 
+//////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of SDMMC
+ */
+#define SOC_SDMMC_CLKS {SOC_MOD_CLK_MPLL}
+
+/**
+ * @brief Type of SDMMC clock source
+ */
+typedef enum {
+    SDMMC_CLK_SRC_DEFAULT = SOC_MOD_CLK_MPLL,   /*!< Select MPLL as the default choice */
+    SDMMC_CLK_SRC_MPLL = SOC_MOD_CLK_MPLL,      /*!< Select MPLL as the source clock */
+} soc_periph_sdmmc_clk_src_t;
+
 /////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32s31/include/soc/soc_caps.h

@@ -89,7 +89,7 @@
 #define SOC_LP_SPI_SUPPORTED            1
 #define SOC_SPIRAM_SUPPORTED            1
 #define SOC_PSRAM_DMA_CAPABLE           1
-// #define SOC_SDMMC_HOST_SUPPORTED        1      // TODO: [ESP32S31] IDF-14705
+#define SOC_SDMMC_HOST_SUPPORTED        1
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_CPU_LOCKUP_DEBUG_SUPPORTED  1
@@ -99,6 +99,7 @@
 #define SOC_SPI_FLASH_SUPPORTED         1         // TODO: [ESP32S31] IDF-14777
 #define SOC_SPI_FLASH_HAS_DEDICATED_LDO 1
 #define SOC_TOUCH_SENSOR_SUPPORTED      1
+#define SOC_GP_LDO_SUPPORTED            1 // General purpose LDO
 #define SOC_RNG_SUPPORTED               1
 #define SOC_PPA_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
@@ -301,6 +302,16 @@
 #define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
 #define SOC_MMU_PER_EXT_MEM_TARGET            (1) /*!< MMU is per physical external memory target (flash, psram) */
 
+/*-------------------------- SDMMC CAPS -----------------------------------------*/
+#define SOC_SDMMC_USE_IOMUX               1
+#define SOC_SDMMC_NUM_SLOTS               2
+#define SOC_SDMMC_DATA_WIDTH_MAX          4
+/* Supported host clock delay phase number */
+#define SOC_SDMMC_DELAY_PHASE_NUM         8
+#define SOC_SDMMC_IO_UHS_POWER_EXTERNAL   1    ///< SDMMC IO power controlled by external power supply
+#define SOC_SDMMC_PSRAM_DMA_CAPABLE       1    ///< SDMMC peripheral can do DMA transfer to/from PSRAMsts
+#define SOC_SDMMC_UHS_I_SUPPORTED         1
+
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  3
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64