From 64bf345683adffe1cdb59a7f5ed015816fb90977 Mon Sep 17 00:00:00 2001 From: hebinglin Date: Thu, 14 May 2026 17:20:22 +0800 Subject: [PATCH 1/6] revert(esp_hw_support): esp32h4 beta5 i2c config retention when pd modem refer to PM-487 --- .../lowpower/port/esp32h4/sleep_clock.c | 20 +++---------------- .../esp32h4/include/soc/Kconfig.soc_caps.in | 4 ---- components/soc/esp32h4/include/soc/soc_caps.h | 1 - 3 files changed, 3 insertions(+), 22 deletions(-) diff --git a/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c index e66cd31aaa9..3ad688d8e5b 100644 --- a/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c @@ -32,14 +32,14 @@ esp_err_t sleep_clock_system_retention_init(void *arg) #undef N_REGS_PCR } -#if CONFIG_MAC_BB_PD || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE || SOC_PM_MODEM_CLK_CONF_RETENTION +#if CONFIG_MAC_BB_PD || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE esp_err_t sleep_clock_modem_retention_init(void *arg) { #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) #define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) /* In ESP32H4, the I2C control registers, syscon is placed in the modem domain, lpcon is placed in the top domain, - and the BBPL requires I2C for calibration. This is the reason why the code for the BPLL enableq + and the BBPL requires I2C for calibration. This is the reason why the code for the BPLL enabled section needs to be placed in this function.*/ const static sleep_retention_entries_config_t modem_regs_retention[] = { /* SYSCON LPCON configuration retention */ @@ -69,9 +69,7 @@ bool clock_domain_pd_allowed(void) * necessary to check the state of CLOCK_MODEM to determine MODEM domain on * or off. The clock and reset of digital peripherals are managed through * PCR, with TOP domain similar to MODEM domain. */ -#if SOC_BLE_SUPPORTED || SOC_IEEE802154_SUPPORTED sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; -#endif #if SOC_BT_SUPPORTED modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BLE_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC % 32); modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); @@ -93,9 +91,6 @@ bool clock_domain_pd_allowed(void) if (!sleep_retention_module_bitmap_eq(modem_modules, null_module)) { mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); } -#endif -#if SOC_PM_MODEM_CLK_CONF_RETENTION - mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); #endif const sleep_retention_module_bitmap_t clock_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask); const sleep_retention_module_bitmap_t clock_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask); @@ -113,21 +108,12 @@ ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) }; sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param); -#if CONFIG_MAC_BB_PD || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE || SOC_PM_MODEM_CLK_CONF_RETENTION +#if CONFIG_MAC_BB_PD || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE init_param = (sleep_retention_module_init_param_t) { .cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } }, -#if !SOC_PM_MODEM_CLK_CONF_RETENTION .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH -#endif }; sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param); #endif -#if SOC_PM_MODEM_CLK_CONF_RETENTION - if (sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_CLOCK_MODEM) != ESP_OK) { - // even though the modem clock retention module create failed, sleep process can be executed without pd the modem domain, so just warning here - ESP_LOGW(TAG, "create retention link failed on modem clock, modem power domain won't be turned off during sleep"); - } -#endif - return ESP_OK; } diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 720161d8b89..5c458345c0c 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -1199,10 +1199,6 @@ config SOC_PM_MODEM_RETENTION_BY_REGDMA bool default y -config SOC_PM_MODEM_CLK_CONF_RETENTION - bool - default y - config SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 0d3d288b713..9ab71a88543 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -507,7 +507,6 @@ #define SOC_PM_CPU_RETENTION_BY_SW (1) #define SOC_PM_FPU_RETENTION_BY_SW (1) #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) -#define SOC_PM_MODEM_CLK_CONF_RETENTION (1) /*!< In esp32H4, i2c lpcon is placed in top domain*/ #define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1) #define SOC_PM_PAU_LINK_NUM (4) From f73d67acb27b3a551e9e6d9acc5cee5f284d1492 Mon Sep 17 00:00:00 2001 From: hebinglin Date: Thu, 14 May 2026 17:27:38 +0800 Subject: [PATCH 2/6] revert(esp_hw_support): add modem_lpcon retention for esp32h21 --- .../lowpower/port/esp32h21/sleep_clock.c | 63 +++++++------------ .../lowpower/port/esp32h4/sleep_clock.c | 5 +- .../esp32h21/include/soc/Kconfig.soc_caps.in | 4 -- .../soc/esp32h21/include/soc/soc_caps.h | 1 - 4 files changed, 27 insertions(+), 46 deletions(-) diff --git a/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c index 3060e6adc57..06034e955e3 100644 --- a/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c @@ -6,22 +6,32 @@ #include "esp_private/sleep_clock.h" #include "soc/pcr_reg.h" +#include "modem/i2c_ana_mst_reg.h" #include "modem/modem_syscon_reg.h" #include "modem/modem_lpcon_reg.h" -#include "modem/i2c_ana_mst_reg.h" -#include "soc/pmu_reg.h" -#include "soc/lp_analog_peri_reg.h" + ESP_LOG_ATTR_TAG(TAG, "sleep_clock"); esp_err_t sleep_clock_system_retention_init(void *arg) { #define N_REGS_PCR() (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1) + const static sleep_retention_entries_config_t pcr_regs_retention[] = { + /* Enable i2c master clock */ + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, + /* Start BBPLL self-calibration */ + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + /* Wait calibration done */ + [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, + /* Stop BBPLL self-calibration */ + [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, /* Clock configuration retention */ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, - [2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); @@ -32,29 +42,18 @@ esp_err_t sleep_clock_system_retention_init(void *arg) #undef N_REGS_PCR } -#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE || SOC_PM_MODEM_CLK_CONF_RETENTION +#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE esp_err_t sleep_clock_modem_retention_init(void *arg) { #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) #define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) - /* In ESP32H21, the I2C control registers, syscon is placed in the modem domain, lpcon is placed in the top domain, - and the BBPL requires I2C for calibration. This is the reason why the code for the BPLL enableq - section needs to be placed in this function.*/ + /* In ESP32H21, the I2C control registers (syscon, lpcon) are placed in the modem domain, + and the BBPL requires I2C for calibration. This is the reason why the code for the BPLL enabled + section needs to be placed in this function.*/ const static sleep_retention_entries_config_t modem_regs_retention[] = { - /* SYSCON LPCON configuration retention */ - [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK (0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM LPCON */ - /* Enable i2c master clock */ - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(1), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, - /* Start BBPLL self-calibration */ - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, - /* Wait calibration done */ - [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_MODEMSYSCON_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, - /* Stop BBPLL self-calibration */ - [6] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_MODEMSYSCON_LINK(6), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM LPCON */ }; esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM); @@ -79,9 +78,7 @@ bool clock_domain_pd_allowed(void) * necessary to check the state of CLOCK_MODEM to determine MODEM domain on * or off. The clock and reset of digital peripherals are managed through * PCR, with TOP domain similar to MODEM domain. */ -#if SOC_BLE_SUPPORTED || SOC_IEEE802154_SUPPORTED - sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; -#endif + __attribute__((unused)) sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; #if SOC_BT_SUPPORTED modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BLE_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC % 32); modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); @@ -103,9 +100,6 @@ bool clock_domain_pd_allowed(void) if (!sleep_retention_module_bitmap_eq(modem_modules, null_module)) { mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); } -#endif -#if SOC_PM_MODEM_CLK_CONF_RETENTION - mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); #endif const sleep_retention_module_bitmap_t clock_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask); const sleep_retention_module_bitmap_t clock_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask); @@ -123,21 +117,12 @@ ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) }; sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param); -#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE || SOC_PM_MODEM_CLK_CONF_RETENTION +#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE init_param = (sleep_retention_module_init_param_t) { .cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } }, -#if !SOC_PM_MODEM_CLK_CONF_RETENTION .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH -#endif }; sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param); #endif -#if SOC_PM_MODEM_CLK_CONF_RETENTION - if (sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_CLOCK_MODEM) != ESP_OK) { - // even though the modem clock retention module create failed, sleep process can be executed without pd the modem domain, so just warning here - ESP_LOGW(TAG, "create retention link failed on modem clock, modem power domain won't be turned off during sleep"); - } -#endif - return ESP_OK; } diff --git a/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c index 3ad688d8e5b..6afeaa6e365 100644 --- a/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c @@ -38,9 +38,10 @@ esp_err_t sleep_clock_modem_retention_init(void *arg) #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) #define N_REGS_LPCON() (((MODEM_LPCON_MEM_CONF_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) - /* In ESP32H4, the I2C control registers, syscon is placed in the modem domain, lpcon is placed in the top domain, + /* In ESP32H4, the I2C control registers (syscon, lpcon) are placed in the modem domain, and the BBPL requires I2C for calibration. This is the reason why the code for the BPLL enabled section needs to be placed in this function.*/ + /* SYSCON LPCON configuration retention */ const static sleep_retention_entries_config_t modem_regs_retention[] = { /* SYSCON LPCON configuration retention */ [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ @@ -69,7 +70,7 @@ bool clock_domain_pd_allowed(void) * necessary to check the state of CLOCK_MODEM to determine MODEM domain on * or off. The clock and reset of digital peripherals are managed through * PCR, with TOP domain similar to MODEM domain. */ - sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; + __attribute__((unused)) sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; #if SOC_BT_SUPPORTED modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BLE_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC % 32); modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index c3d02014d64..ea8bec986e0 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -1011,10 +1011,6 @@ config SOC_PM_MODEM_RETENTION_BY_REGDMA bool default y -config SOC_PM_MODEM_CLK_CONF_RETENTION - bool - default y - config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY bool default y diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 2f6debcc12d..d05035b4157 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -463,7 +463,6 @@ #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1) #define SOC_PM_CPU_RETENTION_BY_SW (1) #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) -#define SOC_PM_MODEM_CLK_CONF_RETENTION (1) /*!< In esp32H21, i2c lpcon is placed in top domain*/ #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*! Date: Fri, 15 May 2026 14:19:53 +0800 Subject: [PATCH 3/6] change(esp_hw_support): add i2c_mst_st_map and lp_apb_st_map in h4 i2c_mst enable way --- components/esp_hal_pmu/include/hal/pmu_types.h | 12 ++++++++++++ .../esp32h4/include/hal/regi2c_ctrl_ll.h | 8 ++++++++ .../esp_hw_support/include/esp_private/esp_pmu.h | 11 +---------- .../esp_hw_support/include/esp_private/sleep_clock.h | 2 +- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/components/esp_hal_pmu/include/hal/pmu_types.h b/components/esp_hal_pmu/include/hal/pmu_types.h index 77767dd8f54..8b8ace4e051 100644 --- a/components/esp_hal_pmu/include/hal/pmu_types.h +++ b/components/esp_hal_pmu/include/hal/pmu_types.h @@ -7,6 +7,7 @@ #pragma once #include +#include "soc/soc.h" #include "soc/soc_caps.h" #include "hal/config.h" @@ -24,6 +25,17 @@ typedef enum { PMU_MODE_HP_MAX, } pmu_hp_mode_t; +/** + * @brief PMU ICG modem code of HP system + * + * Each code maps to one bit in modem_lpcon `clk_*_st_map` bitmap fields. + */ +typedef enum { + PMU_HP_ICG_MODEM_CODE_SLEEP = 0, /*!< ICG bitmap bit for HP_SLEEP mode */ + PMU_HP_ICG_MODEM_CODE_MODEM = 1, /*!< ICG bitmap bit for HP_MODEM mode */ + PMU_HP_ICG_MODEM_CODE_ACTIVE = 2, /*!< ICG bitmap bit for HP_ACTIVE mode */ +} pmu_hp_icg_modem_mode_t; + /** * @brief PMU modes of LP system */ diff --git a/components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h b/components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h index ff476dabb4b..d0941de6d81 100644 --- a/components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h +++ b/components/esp_hal_regi2c/esp32h4/include/hal/regi2c_ctrl_ll.h @@ -12,6 +12,10 @@ #include "soc/pmu_reg.h" #include "modem/modem_lpcon_struct.h" #include "modem/modem_syscon_struct.h" +#include "hal/modem_lpcon_ll.h" +#if SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG +#include "hal/pmu_types.h" +#endif #ifdef __cplusplus extern "C" { @@ -24,6 +28,10 @@ extern "C" { */ static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en) { + /* In ESP32H4, modem_lpcon_reg will lose power after sleep with top pd, so we need to set i2c master and lp_apb clock active and modem st map */ + const uint32_t icg_bitmap = BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE) | BIT(PMU_HP_ICG_MODEM_CODE_MODEM); + modem_lpcon_ll_set_i2c_master_icg_bitmap(&MODEM_LPCON, icg_bitmap); + modem_lpcon_ll_set_lp_apb_icg_bitmap(&MODEM_LPCON, icg_bitmap); MODEM_LPCON.clk_conf.clk_i2c_mst_en = en; } diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 2846bc34390..928f1a4ea90 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -13,6 +13,7 @@ #include "soc/soc_caps.h" #include "soc/clk_tree_defs.h" +#include "hal/pmu_types.h" #if SOC_PMU_SUPPORTED #include "hal/pmu_hal.h" @@ -24,16 +25,6 @@ extern "C" { #endif -/** - * @brief PMU ICG modem code of HP system - * @note This type is required in rtc_clk_init.c when PMU not fully supported - */ -typedef enum { - PMU_HP_ICG_MODEM_CODE_SLEEP = 0, - PMU_HP_ICG_MODEM_CODE_MODEM = 1, - PMU_HP_ICG_MODEM_CODE_ACTIVE = 2, -} pmu_hp_icg_modem_mode_t; - #if SOC_PMU_SUPPORTED #define RTC_SLEEP_PD_DIG PMU_SLEEP_PD_TOP //!< Deep sleep (power down digital domain, includes all power domains diff --git a/components/esp_hw_support/include/esp_private/sleep_clock.h b/components/esp_hw_support/include/esp_private/sleep_clock.h index 60b5a715027..cdaf844a1eb 100644 --- a/components/esp_hw_support/include/esp_private/sleep_clock.h +++ b/components/esp_hw_support/include/esp_private/sleep_clock.h @@ -51,7 +51,7 @@ bool clock_domain_pd_allowed(void); */ esp_err_t sleep_clock_system_retention_init(void *arg); -#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE || SOC_PM_MODEM_CLK_CONF_RETENTION +#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE /** * @brief Modem system clock retention initialize. * From 14b1e9e3b303687f0d9c614a1c1a8713c77d8cc6 Mon Sep 17 00:00:00 2001 From: hebinglin Date: Thu, 21 May 2026 20:53:39 +0800 Subject: [PATCH 4/6] revert(ci): fix the ci issue of Test target MISMATCH by esp32h21 --- components/esp_driver_rmt/test_apps/.build-test-rules.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_driver_rmt/test_apps/.build-test-rules.yml b/components/esp_driver_rmt/test_apps/.build-test-rules.yml index 1c644a6c78a..9450905225d 100644 --- a/components/esp_driver_rmt/test_apps/.build-test-rules.yml +++ b/components/esp_driver_rmt/test_apps/.build-test-rules.yml @@ -4,7 +4,7 @@ components/esp_driver_rmt/test_apps/rmt: disable: - if: SOC_RMT_SUPPORTED != 1 disable_test: - - if: IDF_TARGET in ["esp32h21"] + - if: IDF_TARGET in ["esp32h4"] temporary: true reason: BLE power save bringup is not done depends_components: From 9d59b0073466b67d909fce2fe282d136931c5c12 Mon Sep 17 00:00:00 2001 From: hebinglin Date: Thu, 21 May 2026 20:54:23 +0800 Subject: [PATCH 5/6] revert(ci): fix the ci issue Test target MISMATCH --- components/esp_driver_ledc/test_apps/.build-test-rules.yml | 4 ---- components/esp_driver_mcpwm/test_apps/.build-test-rules.yml | 4 ---- components/esp_driver_rmt/test_apps/.build-test-rules.yml | 4 ---- components/esp_driver_sdm/test_apps/.build-test-rules.yml | 4 ---- 4 files changed, 16 deletions(-) diff --git a/components/esp_driver_ledc/test_apps/.build-test-rules.yml b/components/esp_driver_ledc/test_apps/.build-test-rules.yml index 4a4d8d46126..e98bab30649 100644 --- a/components/esp_driver_ledc/test_apps/.build-test-rules.yml +++ b/components/esp_driver_ledc/test_apps/.build-test-rules.yml @@ -3,10 +3,6 @@ components/esp_driver_ledc/test_apps/ledc: disable: - if: SOC_LEDC_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32h4"] - temporary: true - reason: BLE power save bringup is not done depends_components: - esp_driver_ledc - esp_hal_ledc diff --git a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml index 474af4efadf..c3027046e53 100644 --- a/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml +++ b/components/esp_driver_mcpwm/test_apps/.build-test-rules.yml @@ -3,10 +3,6 @@ components/esp_driver_mcpwm/test_apps/mcpwm: disable: - if: SOC_MCPWM_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32h4"] - temporary: true - reason: BLE power save bringup is not done depends_components: - esp_driver_mcpwm - esp_hal_mcpwm diff --git a/components/esp_driver_rmt/test_apps/.build-test-rules.yml b/components/esp_driver_rmt/test_apps/.build-test-rules.yml index 9450905225d..dc519798388 100644 --- a/components/esp_driver_rmt/test_apps/.build-test-rules.yml +++ b/components/esp_driver_rmt/test_apps/.build-test-rules.yml @@ -3,10 +3,6 @@ components/esp_driver_rmt/test_apps/rmt: disable: - if: SOC_RMT_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32h4"] - temporary: true - reason: BLE power save bringup is not done depends_components: - esp_driver_rmt - esp_driver_dma diff --git a/components/esp_driver_sdm/test_apps/.build-test-rules.yml b/components/esp_driver_sdm/test_apps/.build-test-rules.yml index cdbacc941c8..1f632d478ae 100644 --- a/components/esp_driver_sdm/test_apps/.build-test-rules.yml +++ b/components/esp_driver_sdm/test_apps/.build-test-rules.yml @@ -3,10 +3,6 @@ components/esp_driver_sdm/test_apps/sigma_delta: disable: - if: SOC_SDM_SUPPORTED != 1 - disable_test: - - if: IDF_TARGET in ["esp32h4"] - temporary: true - reason: BLE power save bringup is not done depends_components: - esp_driver_gpio - esp_driver_sdm From fa5132aa2f6a9c6cb20bffe12d548319b4e50a46 Mon Sep 17 00:00:00 2001 From: hebinglin Date: Thu, 21 May 2026 20:54:59 +0800 Subject: [PATCH 6/6] revert(ci): fix top domain power down not allow caused by ble power save not done --- .../esp_driver_gptimer/test_apps/gptimer/pytest_gptimer.py | 1 - components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py | 1 - components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py | 1 - components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py | 1 - .../esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py | 1 - 5 files changed, 5 deletions(-) diff --git a/components/esp_driver_gptimer/test_apps/gptimer/pytest_gptimer.py b/components/esp_driver_gptimer/test_apps/gptimer/pytest_gptimer.py index 246c934a2ed..041a83c36f3 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/pytest_gptimer.py +++ b/components/esp_driver_gptimer/test_apps/gptimer/pytest_gptimer.py @@ -7,7 +7,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets @pytest.mark.generic -@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='BLE power save bringup is not done') @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py index 84e2be2efff..2a4453af593 100644 --- a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py +++ b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py @@ -7,7 +7,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets @pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='skip due to duplication with test_ledc_psram') -@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='BLE power save bringup is not done') @pytest.mark.generic @pytest.mark.parametrize( 'config', diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py index bd4f9cded61..597caef05eb 100644 --- a/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py +++ b/components/esp_driver_mcpwm/test_apps/mcpwm/pytest_mcpwm.py @@ -6,7 +6,6 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic -@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='BLE power save bringup is not done') @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py index 2c8ae27286a..af2479efcb5 100644 --- a/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py +++ b/components/esp_driver_rmt/test_apps/rmt/pytest_rmt.py @@ -7,7 +7,6 @@ from pytest_embedded_idf.utils import soc_filtered_targets @pytest.mark.generic -@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='BLE power save bringup is not done') @pytest.mark.parametrize( 'config', [ diff --git a/components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py b/components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py index f4b39199e46..efd82d173ad 100644 --- a/components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py +++ b/components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py @@ -12,7 +12,6 @@ CONFIGS = [ @pytest.mark.generic -@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='BLE power save bringup is not done') @pytest.mark.parametrize('config', CONFIGS, indirect=True) @idf_parametrize( 'target',