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clk_tree: added default clock source for peripheral
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@@ -89,7 +89,7 @@ void app_main(void)
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esp_lcd_rgb_panel_config_t panel_config = {
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.data_width = 16, // RGB565 in parallel mode, thus 16bit in width
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.psram_trans_align = 64,
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.clk_src = LCD_CLK_SRC_PLL160M,
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.clk_src = LCD_CLK_SRC_DEFAULT,
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.disp_gpio_num = EXAMPLE_PIN_NUM_DISP_EN,
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.pclk_gpio_num = EXAMPLE_PIN_NUM_PCLK,
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.vsync_gpio_num = EXAMPLE_PIN_NUM_VSYNC,
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