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Merge branch 'bugfix/h21_cpu_test' into 'master'

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fix(riscv): use CSR 0xC10 for privilege mode on ESP32-H21

See merge request espressif/esp-idf!52924
This commit is contained in:
Marius Vikhammer
2026-09-18 11:39:48 +08:00
parent bd0820d403 f4d37c0054
commit f2cddffb53
1 changed files with 1 additions and 1 deletions
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2
components/riscv/include/riscv/csr.h
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@@ -203,7 +203,7 @@ extern "C" {
#define STPC2 0xBF2
/* Espressif's custom CSR for the current privilege mode */
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21
#define CSR_PRV_MODE 0xC10
#else
#define CSR_PRV_MODE 0x810