diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c
index 900585a398d..1686306124d 100644
--- a/components/bootloader_support/src/bootloader_common_loader.c
+++ b/components/bootloader_support/src/bootloader_common_loader.c
@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "string.h"
+#include <stdint.h>
 #include "sdkconfig.h"
 #include "esp_err.h"
 #include "esp_log.h"
@@ -277,7 +278,9 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
 #endif //ESP_ROM_HAS_LP_ROM
 
 #if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
-    static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR - ESP_SECURE_BOOT_DIGEST_LEN;
+    /* ROM stores the verified image digest in the last ESP_SECURE_BOOT_DIGEST_LEN
+     * bytes of LP/RTC RAM on deep-sleep wake. Keep retain mem below that region. */
+    static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)((uintptr_t)RTC_RETAIN_MEM_ADDR - ESP_SECURE_BOOT_DIGEST_LEN);
 #else
     static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR;
 #endif
diff --git a/components/esp_rom/esp32s31/Kconfig.soc_caps.in b/components/esp_rom/esp32s31/Kconfig.soc_caps.in
index 83db14746f3..bf9685344c0 100644
--- a/components/esp_rom/esp32s31/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32s31/Kconfig.soc_caps.in
@@ -98,3 +98,7 @@ config ESP_ROM_BOOTLOADER_OFFSET_FLASH
 config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP
     bool
     default y
+
+config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+    bool
+    default y
diff --git a/components/esp_rom/esp32s31/esp_rom_caps.h b/components/esp_rom/esp32s31/esp_rom_caps.h
index b4499994a0e..99a0312f9fc 100644
--- a/components/esp_rom/esp32s31/esp_rom_caps.h
+++ b/components/esp_rom/esp32s31/esp_rom_caps.h
@@ -31,3 +31,4 @@
 #define ESP_ROM_PRINTS_LOCKUP_STATUS        (1) // ROM bootloader already prints CPU lockup diagnostic status
 #define ESP_ROM_BOOTLOADER_OFFSET_FLASH     (0x2000) // Bootloader offset in flash determined by the ROM bootloader
 #define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, need map parameter
+#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
diff --git a/components/esp_system/ld/esp32s31/memory.ld.in b/components/esp_system/ld/esp32s31/memory.ld.in
index 666eca55342..8cdbe2224b6 100644
--- a/components/esp_system/ld/esp32s31/memory.ld.in
+++ b/components/esp_system/ld/esp32s31/memory.ld.in
@@ -64,6 +64,42 @@ MEMORY
   /* (See irom_seg for meaning of 0x20 offset in the above.) */
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
+  /**
+ *  LP RAM (RTC Memory) Layout for ESP32-S31
+ *  Total Size: 32KB (0x8000)
+ *  Address Range: 0x2E000000 - 0x2E008000
+ *
+ *  ESP32-S31 has only unified LP RAM (no separate RTC FAST/SLOW).
+ *  The LP RAM persists over deep sleep and is used for:
+ *  - ULP coprocessor code and data (optional)
+ *  - RTC wake stub code and data
+ *  - Data that needs to survive deep sleep
+ *  - Bootloader retain memory (for reboot counter, OTA info, etc.)
+ *
+ *  +-----------------------------+ 0x2E008000 (LP RAM end)
+ *  | Secure Boot Image Digest    | ( For ROM using, must keep it at the end ESP_SECURE_BOOT_DIGEST_LEN bytes of LP RAM)
+ *  | for fast wake secure boot.  |
+ *  |(only if CONFIG_SECURE_BOOT) |
+ *  |- - - - - - - - - - - - - - -|
+ *  | bootloader_data_rtc_mem     |
+ *  | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM)
+ *  |- - - - - - - - - - - - - - -|
+ *  | rtc_timer_data_in_rtc_mem   |
+ *  | (RTC_TIMER_RESERVE_RTC=24B) |
+ *  +-----------------------------+ 0x2E008000 - RESERVE_RTC_MEM
+ *  | .rtc.force_slow             |
+ *  | .rtc_noinit (NOLOAD)        |
+ *  | .rtc.bss (NOLOAD)           |
+ *  | .rtc.data                   | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg)
+ *  | .rtc.force_fast             |
+ *  |- - - - - - - - - - - - - - -|
+ *  | .rtc.text                   | RTC wake stub code
+ *  +-----------------------------+ 0x2E000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled)
+ *  | ULP Coprocessor Reserve     | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM)
+ *  | (code + data)               |
+ *  +-----------------------------+ 0x2E000000 (LP RAM start)
+ */
+
   /**
    * lp ram memory (RWX). Persists over deep sleep.
    */
diff --git a/components/heap/port/esp32s31/memory_layout.c b/components/heap/port/esp32s31/memory_layout.c
index 90040ea191a..ad986799012 100644
--- a/components/heap/port/esp32s31/memory_layout.c
+++ b/components/heap/port/esp32s31/memory_layout.c
@@ -9,6 +9,7 @@
 #include "esp_attr.h"
 #include "sdkconfig.h"
 #include "soc/soc.h"
+#include "esp_rom_caps.h"
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
 
@@ -67,6 +68,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
  */
 #define APP_USABLE_DRAM_END                 (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
+#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
+#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
+#define ESP_SECURE_BOOT_DIGEST_LEN 48
+#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+#define ESP_SECURE_BOOT_DIGEST_LEN 32
+#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
+
+#define APP_USABLE_RTC_MEM_END              (SOC_LP_RAM_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
+#else
+#define APP_USABLE_RTC_MEM_END              (SOC_LP_RAM_HIGH)
+#endif
 
 const soc_memory_region_t soc_memory_regions[] = {
 #ifdef CONFIG_SPIRAM
@@ -75,7 +87,7 @@ const soc_memory_region_t soc_memory_regions[] = {
     { SOC_DIRAM_DRAM_LOW,   (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW),     SOC_MEMORY_TYPE_RAM,    SOC_DIRAM_IRAM_LOW,     false}, //D/IRAM, can be used as trace memory
     { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DRAM_END),    SOC_MEMORY_TYPE_RAM,    APP_USABLE_DRAM_END,    true},  //D/IRAM, can be used as trace memory (ROM reserved area)
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { SOC_LP_RAM_LOW,           (SOC_LP_RAM_HIGH - SOC_LP_RAM_LOW),                 SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
+    { SOC_LP_RAM_LOW,       (APP_USABLE_RTC_MEM_END - SOC_LP_RAM_LOW),      SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
 #endif
 };