From f1f3f204fe8d4c17d5b377be978d364be53244b7 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 6 May 2026 16:25:57 +0800 Subject: [PATCH] feat(esp_hw_support): support esp32s31 lightsleep/deepsleep example --- .../test_apps/uart/main/test_hp_uart_wakeup.c | 2 +- .../esp32s31/include/hal/clk_gate_ll.h | 38 +++++++++++++++++++ .../esp_hal_pmu/esp32s31/include/hal/pmu_ll.h | 1 + .../esp_hw_support/port/esp32s31/rtc_clk.c | 21 ++++------ components/esp_hw_support/sleep_modem.c | 2 +- components/esp_hw_support/sleep_modes.c | 15 +++++++- components/esp_hw_support/sleep_usb.c | 14 ++++--- .../test_apps/sleep_retention/README.md | 4 +- .../test_apps/wakeup_tests/README.md | 4 +- components/esp_pm/linker.lf | 2 +- components/esp_system/port/cpu_start.c | 11 +++--- .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 ++ components/soc/esp32p4/include/soc/soc_caps.h | 1 + .../esp32s31/include/soc/Kconfig.soc_caps.in | 26 ++++++++----- .../soc/esp32s31/include/soc/soc_caps.h | 13 +++---- examples/system/deep_sleep/README.md | 4 +- .../system/deep_sleep/main/Kconfig.projbuild | 1 + .../system/deep_sleep/pytest_deep_sleep.py | 1 - examples/system/light_sleep/README.md | 4 +- .../system/light_sleep/main/gpio_wakeup.c | 2 + .../system/light_sleep/pytest_light_sleep.py | 1 - examples/system/ulp/lp_core/gpio/README.md | 4 +- .../lp_core/gpio_intr_pulse_counter/README.md | 4 +- .../system/ulp/lp_core/gpio_wakeup/README.md | 4 +- examples/system/ulp/lp_core/lp_spi/README.md | 4 +- .../system/ulp/lp_core/lp_touch/README.md | 4 +- .../lp_uart/lp_uart_char_seq_wakeup/README.md | 4 +- .../lp_core/lp_uart/lp_uart_echo/README.md | 4 +- .../lp_core/lp_uart/lp_uart_print/README.md | 4 +- 29 files changed, 132 insertions(+), 71 deletions(-) create mode 100644 components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h diff --git a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c index f85c7cba374..91e93568bc3 100644 --- a/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c +++ b/components/esp_driver_uart/test_apps/uart/main/test_hp_uart_wakeup.c @@ -36,7 +36,7 @@ #elif CONFIG_IDF_TARGET_ESP32C61 #define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_4 #define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_5 -#elif CONFIG_IDF_TARGET_ESP32C5 +#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32S31 #define DEFAULT_UART1_TX_IO_NUM GPIO_NUM_2 #define DEFAULT_UART1_RX_IO_NUM GPIO_NUM_3 #elif CONFIG_IDF_TARGET_ESP32H21 diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h new file mode 100644 index 00000000000..60942aaf86e --- /dev/null +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_attr.h" +#include "soc/soc.h" +#include "soc/reset_reasons.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/lp_clkrst_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enable or disable the clock gate for rtc fast to lp periph + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable) +{ + LP_CLKRST.root_clk_conf.fosc_clk_force_on = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_rtc_fast_to_lp_periph_en(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _clk_gate_ll_rtc_fast_to_lp_periph_en(__VA_ARGS__); \ + } while(0) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h b/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h index 15192392543..b120ba0815c 100644 --- a/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h +++ b/components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h @@ -795,6 +795,7 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_ext1_get_wakeup_status(void) FORCE_INLINE_ATTR void pmu_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(PMU_EXT_WAKEUP_CNTL_REG, PMU_EXT_WAKEUP_STATUS_CLR); + REG_CLR_BIT(PMU_EXT_WAKEUP_CNTL_REG, PMU_EXT_WAKEUP_STATUS_CLR); } /** diff --git a/components/esp_hw_support/port/esp32s31/rtc_clk.c b/components/esp_hw_support/port/esp32s31/rtc_clk.c index d463ec6e358..ac4f2813c04 100644 --- a/components/esp_hw_support/port/esp32s31/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s31/rtc_clk.c @@ -15,6 +15,7 @@ #include "esp_private/rtc_clk.h" #include "esp_hw_log.h" #include "esp_rom_sys.h" +#include "esp_sleep.h" #include "hal/clk_tree_ll.h" #include "esp_private/sleep_event.h" #include "esp_private/regi2c_ctrl.h" @@ -87,19 +88,13 @@ void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) { clk_ll_rtc_slow_set_src(clk_src); esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH); - // TODO: IDF-14645 -// #ifndef BOOTLOADER_BUILD -// if (clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { -// esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_ON); -// } else { -// esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); -// } -// if (clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { -// esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_ON); -// } else { -// esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); -// } -// #endif +#ifndef BOOTLOADER_BUILD + if (clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_ON); + } else { + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); + } +#endif } soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c index 1bffcf6129e..fb318afd660 100644 --- a/components/esp_hw_support/sleep_modem.c +++ b/components/esp_hw_support/sleep_modem.c @@ -225,7 +225,7 @@ uint32_t sleep_modem_reject_triggers(void) { uint32_t reject_triggers = 0; #if SOC_PM_SUPPORT_PMU_MODEM_STATE - reject_triggers = (s_sleep_modem.wifi.phy_link != NULL) ? BIT(16) : 0; + reject_triggers = (s_sleep_modem.wifi.phy_link != NULL) ? PMU_MODEM_WAKEUP_PROTECT : 0; #endif return reject_triggers; } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 3731b1e4097..6b2f04bead4 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -146,6 +146,10 @@ #include "esp32p4/rom/rtc.h" #include "hal/gpio_ll.h" #include "hal/clk_gate_ll.h" +#elif CONFIG_IDF_TARGET_ESP32S31 +#include "esp32s31/rom/rtc.h" +#include "hal/gpio_ll.h" +#include "hal/clk_gate_ll.h" #endif #if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX @@ -245,6 +249,9 @@ #define DEFAULT_SLEEP_OUT_OVERHEAD_US (324) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (240) #define LDO_POWER_TAKEOVER_PREPARATION_TIME_US (185) +#elif CONFIG_IDF_TARGET_ESP32S31 +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (324) +#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (240) #endif // Actually costs 80us, using the fastest slow clock 150K calculation takes about 16 ticks @@ -694,7 +701,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool // Only avoid USJ pad leakage here, USB OTG pad leakage is prevented through USB Host driver. sleep_console_usj_pad_backup_and_disable(); #endif -#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD +#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD && SOC_USB_OTG_NEED_SOFTWARE_SUSPEND_BEFORE_SLEEP if (!(sleep_flags & PMU_SLEEP_PD_CNNT)) { sleep_usb_otg_phy_backup_and_disable(); } @@ -715,7 +722,11 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool /* When using SPIRAM on the ESP32-C5, we need to use Cache_WriteBack_All to protect SPIRAM data because the cache powers down when we power down the CPU */ if(sleep_flags & PMU_SLEEP_PD_CPU) { + #if SOC_SHARED_IDCACHE_SUPPORTED || CONFIG_IDF_TARGET_ESP32H4 Cache_WriteBack_All(); +#else + Cache_WriteBack_All(CACHE_MAP_L1_DCACHE); +#endif } #endif #if ADC_LL_ANA_CALI_REG_PD_WORKAROUND @@ -762,7 +773,7 @@ static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags) #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP sleep_console_usj_pad_restore(); #endif -#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD +#if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD && SOC_USB_OTG_NEED_SOFTWARE_SUSPEND_BEFORE_SLEEP if (!(sleep_flags & PMU_SLEEP_PD_CNNT)) { sleep_usb_otg_phy_restore(); } diff --git a/components/esp_hw_support/sleep_usb.c b/components/esp_hw_support/sleep_usb.c index d672fa2343a..9888a6b854f 100644 --- a/components/esp_hw_support/sleep_usb.c +++ b/components/esp_hw_support/sleep_usb.c @@ -20,18 +20,20 @@ void sleep_usb_otg_phy_backup_and_disable(void) if (!s_usb_utmi_bus_clock_state) { _usb_utmi_ll_enable_bus_clock(true); } + usb_dwc_dev_t *hw = USB_DWC_LL_GET_HW(0); // Forcing BVALID low to ignore the hardware-detected VBUS BVALID signal to suppress USB leakage. - s_usb_dwc_bvalid_override = usb_dwc_ll_get_bvalid_override(&USB_DWC_HS); - usb_dwc_ll_enable_bvalid_override(&USB_DWC_HS, true); - s_usb_utmi_stoppclk_state = usb_dwc_ll_get_stoppclk_st(&USB_DWC_HS); - usb_dwc_ll_set_stoppclk(&USB_DWC_HS, true); + s_usb_dwc_bvalid_override = usb_dwc_ll_get_bvalid_override(hw); + usb_dwc_ll_enable_bvalid_override(hw, true); + s_usb_utmi_stoppclk_state = usb_dwc_ll_get_stoppclk_st(hw); + usb_dwc_ll_set_stoppclk(hw, true); } void sleep_usb_otg_phy_restore(void) { _usb_utmi_ll_enable_bus_clock(true); - usb_dwc_ll_enable_bvalid_override(&USB_DWC_HS, s_usb_dwc_bvalid_override); - usb_dwc_ll_set_stoppclk(&USB_DWC_HS, s_usb_utmi_stoppclk_state); + usb_dwc_dev_t *hw = USB_DWC_LL_GET_HW(0); + usb_dwc_ll_enable_bvalid_override(hw, s_usb_dwc_bvalid_override); + usb_dwc_ll_set_stoppclk(hw, s_usb_utmi_stoppclk_state); if (!s_usb_utmi_bus_clock_state) { _usb_utmi_ll_enable_bus_clock(false); } diff --git a/components/esp_hw_support/test_apps/sleep_retention/README.md b/components/esp_hw_support/test_apps/sleep_retention/README.md index b366edfca53..fb2ccc2ca3e 100644 --- a/components/esp_hw_support/test_apps/sleep_retention/README.md +++ b/components/esp_hw_support/test_apps/sleep_retention/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | -| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | --------- | diff --git a/components/esp_hw_support/test_apps/wakeup_tests/README.md b/components/esp_hw_support/test_apps/wakeup_tests/README.md index 44f3780f1d6..d76348d52c2 100644 --- a/components/esp_hw_support/test_apps/wakeup_tests/README.md +++ b/components/esp_hw_support/test_apps/wakeup_tests/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf index 13432b5e366..ae69c7c2858 100644 --- a/components/esp_pm/linker.lf +++ b/components/esp_pm/linker.lf @@ -40,7 +40,7 @@ entries: esp_clk:esp_clk_private_unlock (noflash) if SOC_SYSTIMER_SUPPORTED = y: systimer (noflash) - if IDF_TARGET_ESP32H21 != y && IDF_TARGET_ESP32H4 != y: + if SOC_ADC_SUPPORTED = y: sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash) sar_periph_ctrl:adc_reset_lock_acquire (noflash) sar_periph_ctrl:adc_reset_lock_release (noflash) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 05cf7e5c677..752e9eef304 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -569,14 +569,15 @@ FORCE_INLINE_ATTR IRAM_ATTR void ext_mem_init(void) MSPI_INIT_ATTR void sys_rtc_init(const soc_reset_reason_t *rst_reas) { #if SOC_RTC_WDT_SUPPORTED -#if CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32S31 #define RWDT_RESET RESET_REASON_CORE_RWDT -#define MWDT_RESET RESET_REASON_CORE_MWDT -#elif CONFIG_IDF_TARGET_ESP32S31 -#define RWDT_RESET RESET_REASON_CORE_RWDT -#define MWDT_RESET RESET_REASON_CORE_MWDT0 #else #define RWDT_RESET RESET_REASON_CORE_RTC_WDT +#endif + +#if CONFIG_IDF_TARGET_ESP32P4 +#define MWDT_RESET RESET_REASON_CORE_MWDT +#else #define MWDT_RESET RESET_REASON_CORE_MWDT0 #endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 22f0913e4eb..984a7fa3f61 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1171,6 +1171,10 @@ config SOC_USB_FSLS_PHY_NUM int default 1 +config SOC_USB_OTG_NEED_SOFTWARE_SUSPEND_BEFORE_SLEEP + bool + default y + config SOC_USB_UTMI_PHY_NUM int default 1 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 72976610f36..10193dc3fdb 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -432,6 +432,7 @@ // USB OTG Caps #define SOC_USB_OTG_PERIPH_NUM (2U) #define SOC_USB_FSLS_PHY_NUM (1U) +#define SOC_USB_OTG_NEED_SOFTWARE_SUSPEND_BEFORE_SLEEP (1) // USB PHY Caps #define SOC_USB_UTMI_PHY_NUM (1U) diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index de4d57c63dc..3394abd65c2 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -235,6 +235,14 @@ config SOC_PPA_SUPPORTED bool default y +config SOC_LIGHT_SLEEP_SUPPORTED + bool + default y + +config SOC_DEEP_SLEEP_SUPPORTED + bool + default y + config SOC_MODEM_CLOCK_SUPPORTED bool default y @@ -303,6 +311,10 @@ config SOC_XTAL_SUPPORT_40M bool default y +config SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN + bool + default y + config SOC_ADC_MAX_CHANNEL_NUM int default 10 @@ -443,6 +455,10 @@ config SOC_GPIO_SUPPORT_ETM bool default y +config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP + bool + default y + config SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE bool default y @@ -459,14 +475,10 @@ config SOC_GPIO_OUT_RANGE_MAX int default 61 -config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK +config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK int default 0 -config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT - int - default 8 - config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y @@ -715,10 +727,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR bool default y -config SOC_MSPI_HAS_INDEPENT_IOMUX - bool - default y - config SOC_MEMSPI_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index f0f75fb525b..914c43ce69d 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -97,8 +97,8 @@ #define SOC_TOUCH_SENSOR_SUPPORTED 1 // #define SOC_RNG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14632 #define SOC_PPA_SUPPORTED 1 -// #define SOC_LIGHT_SLEEP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14645 -// #define SOC_DEEP_SLEEP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14643 +#define SOC_LIGHT_SLEEP_SUPPORTED 1 +#define SOC_DEEP_SLEEP_SUPPORTED 1 #define SOC_MODEM_CLOCK_SUPPORTED 1 // #define SOC_PM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14648 #define SOC_BITSCRAMBLER_SUPPORTED 1 @@ -122,7 +122,8 @@ #define SOC_BT_SUPPORTED 1 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ -#define SOC_XTAL_SUPPORT_40M 1 +#define SOC_XTAL_SUPPORT_40M 1 +#define SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN 1 /*-------------------------- ADC CAPS ----------------------------------------*/ /*!< SAR ADC Module*/ @@ -185,7 +186,7 @@ #define SOC_GPIO_SUPPORT_ETM 1 // GPIO0~7 on ESP32S31 can support chip deep sleep wakeup -// #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) // TODO: [ESP32S31] IDF-14643 +#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP #define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1) @@ -198,8 +199,7 @@ #define SOC_GPIO_IN_RANGE_MAX 61 #define SOC_GPIO_OUT_RANGE_MAX 61 -#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFF) -#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8) +#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | 0xFF) // digital I/O pad powered by VDD3V3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_61, excluding GPIO29/41 which are not bonded) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL << SOC_RTCIO_PIN_COUNT) - 1)) @@ -298,7 +298,6 @@ #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) -#define SOC_MSPI_HAS_INDEPENT_IOMUX 1 #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */ diff --git a/examples/system/deep_sleep/README.md b/examples/system/deep_sleep/README.md index da637e2bba6..296cf07c926 100644 --- a/examples/system/deep_sleep/README.md +++ b/examples/system/deep_sleep/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # Deep Sleep Example diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index 0fd23a8a7e8..2657efb2b88 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -268,6 +268,7 @@ menu "Example Configuration" range 0 7 if IDF_TARGET_ESP32C6 range 0 6 if IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5 range 0 15 if IDF_TARGET_ESP32P4 + range 0 7 if IDF_TARGET_ESP32S31 range 0 5 help Only GPIOs which have RTC functionality (pads that powered by VDD3P3_RTC) can be used, diff --git a/examples/system/deep_sleep/pytest_deep_sleep.py b/examples/system/deep_sleep/pytest_deep_sleep.py index 9e6ef09c3e3..3cb8334c819 100644 --- a/examples/system/deep_sleep/pytest_deep_sleep.py +++ b/examples/system/deep_sleep/pytest_deep_sleep.py @@ -12,7 +12,6 @@ from pytest_embedded_idf.utils import idf_parametrize @idf_parametrize( 'config,target', [('esp32_singlecore', 'esp32'), ('basic', 'supported_targets')], indirect=['config', 'target'] ) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_deep_sleep(dut: Dut) -> None: dut.expect_exact('Enabling timer wakeup, 20s', timeout=10) dut.expect_exact('Not a deep sleep reset') diff --git a/examples/system/light_sleep/README.md b/examples/system/light_sleep/README.md index 6aeb8161ccf..89f3d632cba 100644 --- a/examples/system/light_sleep/README.md +++ b/examples/system/light_sleep/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | # Light Sleep Example diff --git a/examples/system/light_sleep/main/gpio_wakeup.c b/examples/system/light_sleep/main/gpio_wakeup.c index 75778640b83..aac5be4fd62 100644 --- a/examples/system/light_sleep/main/gpio_wakeup.c +++ b/examples/system/light_sleep/main/gpio_wakeup.c @@ -21,6 +21,8 @@ #define BOOT_BUTTON_NUM 35 #elif CONFIG_IDF_TARGET_ESP32H21 #define BOOT_BUTTON_NUM 14 +#elif CONFIG_IDF_TARGET_ESP32S31 +#define BOOT_BUTTON_NUM 61 #else #define BOOT_BUTTON_NUM 0 #endif diff --git a/examples/system/light_sleep/pytest_light_sleep.py b/examples/system/light_sleep/pytest_light_sleep.py index 14b2393521b..dc56b443256 100644 --- a/examples/system/light_sleep/pytest_light_sleep.py +++ b/examples/system/light_sleep/pytest_light_sleep.py @@ -10,7 +10,6 @@ from pytest_embedded_idf.utils import idf_parametrize @pytest.mark.generic @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_light_sleep(dut: Dut) -> None: ENTERING_SLEEP_STR = 'Entering light sleep' EXIT_SLEEP_REGEX = r'Returned from light sleep, reason: (\w+), t=(\d+) ms, slept for (\d+) ms' diff --git a/examples/system/ulp/lp_core/gpio/README.md b/examples/system/ulp/lp_core/gpio/README.md index 363d0b6b6af..d082cf4748d 100644 --- a/examples/system/ulp/lp_core/gpio/README.md +++ b/examples/system/ulp/lp_core/gpio/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | --------- | # LP Core simple example with GPIO Polling: diff --git a/examples/system/ulp/lp_core/gpio_intr_pulse_counter/README.md b/examples/system/ulp/lp_core/gpio_intr_pulse_counter/README.md index c6e3dfd7ed4..3a74ba666bb 100644 --- a/examples/system/ulp/lp_core/gpio_intr_pulse_counter/README.md +++ b/examples/system/ulp/lp_core/gpio_intr_pulse_counter/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | --------- | # LP Core Pulse Counting Example diff --git a/examples/system/ulp/lp_core/gpio_wakeup/README.md b/examples/system/ulp/lp_core/gpio_wakeup/README.md index 66925750726..0f8a94bf4c0 100644 --- a/examples/system/ulp/lp_core/gpio_wakeup/README.md +++ b/examples/system/ulp/lp_core/gpio_wakeup/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | --------- | # ULP-LP-Core simple example with GPIO Interrupt: This example demonstrates how to program the LP-Core coprocessor to wake up from a RTC IO interrupt, instead of waking periodically from the ULP timer. diff --git a/examples/system/ulp/lp_core/lp_spi/README.md b/examples/system/ulp/lp_core/lp_spi/README.md index 0d5f94ccd49..a7a619da935 100644 --- a/examples/system/ulp/lp_core/lp_spi/README.md +++ b/examples/system/ulp/lp_core/lp_spi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-P4 | -| ----------------- | -------- | +| Supported Targets | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | --------- | # LP SPI Example diff --git a/examples/system/ulp/lp_core/lp_touch/README.md b/examples/system/ulp/lp_core/lp_touch/README.md index 868e774980d..b913ce143a8 100644 --- a/examples/system/ulp/lp_core/lp_touch/README.md +++ b/examples/system/ulp/lp_core/lp_touch/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-P4 | -| ----------------- | -------- | +| Supported Targets | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | --------- | # LP Core Touch Sensor example: diff --git a/examples/system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup/README.md b/examples/system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup/README.md index 3dc2d4833a8..4b828286237 100644 --- a/examples/system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup/README.md +++ b/examples/system/ulp/lp_core/lp_uart/lp_uart_char_seq_wakeup/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | --------- | # LP UART specific character sequence wakeup mode Example diff --git a/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md b/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md index daf06d51b0c..f33ac6b136f 100644 --- a/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md +++ b/examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | --------- | # LP UART Echo Example diff --git a/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md b/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md index ca96fdc0a36..0ab370e704d 100644 --- a/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md +++ b/examples/system/ulp/lp_core/lp_uart/lp_uart_print/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S31 | +| ----------------- | -------- | -------- | -------- | --------- | # LP UART Print Example