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feat(esp32p4_eco1): modify cpll and spll config

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chaijie@espressif.com
2024-05-11 11:43:24 +08:00
committed by Xiao Xufeng
parent ea010f84ef
commit f1d1dfd1ef
3 changed files with 55 additions and 22 deletions
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components/esp_hw_support/port/esp32p4/pmu_sleep.c
+6 -2
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@@ -27,6 +27,7 @@
#include "pmu_param.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
#include "hal/efuse_hal.h"
#define HP(state) (PMU_MODE_HP_ ## state)
#define LP(state) (PMU_MODE_LP_ ## state)
@@ -317,8 +318,11 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(void)
}
pmu_sleep_shutdown_ldo();
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
unsigned chip_version = efuse_hal_chip_revision();
if (chip_version == 0) {
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
}
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
}