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feat(lcd): support buffer switch interrupt

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This commit is contained in:
Chen Jichang
2026-06-01 18:28:50 +08:00
parent 3e24f276fa
commit f17bc5d033
34 changed files with 417 additions and 119 deletions
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components/esp_hal_dma/esp32c5/include/hal/ahb_dma_ll.h
+2 -2
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@@ -24,8 +24,8 @@ extern "C" {
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_CHANNEL_MAX_WEIGHT 15 // supported weight levels: [0,15]
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
#define AHB_DMA_LL_TX_EVENT_MASK (0x3F)
// for M2M mode, hardware will automatically assign peri_sel ID depends on the channel number (ch0: 10, ch1: 11, ch2: 12)
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1C00)
components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h
+2 -2
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@@ -24,8 +24,8 @@ extern "C" {
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_CHANNEL_MAX_WEIGHT 15 // supported weight levels: [0,15]
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
#define AHB_DMA_LL_TX_EVENT_MASK (0x3F)
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFE75)
components/esp_hal_dma/esp32h4/include/hal/ahb_dma_ll.h
+2 -2
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@@ -23,8 +23,8 @@ extern "C" {
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
#define AHB_DMA_LL_TX_EVENT_MASK (0x3F)
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC00)
components/esp_hal_dma/esp32p4/include/hal/ahb_dma_ll.h
+2
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@@ -24,6 +24,8 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFAC2)
#define AHB_DMA_LL_RX_EVENT_MASK (0x1F)
#define AHB_DMA_LL_TX_EVENT_MASK (0x0F)
///////////////////////////////////// Common /////////////////////////////////////////
/**
components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h
+44
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@@ -13,6 +13,7 @@
#include "hal/hal_utils.h"
#include "hal/gdma_types.h"
#include "hal/gdma_ll.h"
#include "hal/config.h"
#include "soc/axi_dma_struct.h"
#include "soc/axi_dma_reg.h"
@@ -24,6 +25,13 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
#define AXI_DMA_LL_RX_EVENT_MASK (0x1F)
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT 1
#define AXI_DMA_LL_TX_EVENT_MASK (0x40F)
#else
#define AXI_DMA_LL_TX_EVENT_MASK (0x0F)
#endif
///////////////////////////////////// Common /////////////////////////////////////////
/**
@@ -476,6 +484,42 @@ static inline void axi_dma_ll_tx_restart(axi_dma_dev_t *dev, uint32_t channel)
dev->out[channel].conf.out_link1.outlink_restart_chn = 1;
}
#if AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT
/**
* @brief Request link switch done indication for TX channel
*/
static inline void axi_dma_ll_tx_request_link_switch_event(axi_dma_dev_t *dev, uint32_t channel)
{
switch (channel) {
case 0:
dev->link_switch_state.link_switch_state_ch0 = 1;
break;
case 1:
dev->link_switch_state.link_switch_state_ch1 = 1;
break;
case 2:
dev->link_switch_state.link_switch_state_ch2 = 1;
break;
default:
break;
}
}
#endif
/**
* @brief Check if TX link switch done indication is supported
*/
__attribute__((always_inline))
static inline bool axi_dma_ll_tx_is_link_switch_event_supported(axi_dma_dev_t *dev)
{
(void)dev;
#if AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT
return true;
#else
return false;
#endif
}
/**
* @brief Check if DMA TX descriptor FSM is in IDLE state
*/
components/esp_hal_dma/esp32p4/include/hal/gdma_ll.h
+4 -3
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@@ -26,9 +26,10 @@
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_RX_EVENT_MASK (0x1F)
#define GDMA_LL_TX_EVENT_MASK (0x0F)
// the following event bits are only supported by axi-dma
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define GDMA_LL_EVENT_TX_LINK_SWITCH (1<<10)
#endif
// the following event bits are identical for ahb-dma and axi-dma
#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
components/esp_hal_dma/esp32s31/include/hal/ahb_dma_ll.h
+5 -1
View File
@@ -22,8 +22,12 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x8200)
#define LP_AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFFC)
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
#define AHB_DMA_LL_TX_EVENT_MASK (0x3F)
#define LP_AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFFC)
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
#define AHB_DMA_LL_TX_EVENT_MASK (0x3F)
///////////////////////////////////// Common /////////////////////////////////////////
/**
components/esp_hal_dma/esp32s31/include/hal/axi_dma_ll.h
+33
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@@ -24,6 +24,9 @@ extern "C" {
// any "dummy" peripheral ID can be used for M2M mode
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
#define AXI_DMA_LL_RX_EVENT_MASK (0x7F)
#define AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT 1
#define AXI_DMA_LL_TX_EVENT_MASK (0x43F)
///////////////////////////////////// Common /////////////////////////////////////////
/**
@@ -473,6 +476,36 @@ static inline void axi_dma_ll_tx_restart(axi_dma_dev_t *dev, uint32_t channel)
dev->out[channel].conf.out_link1.outlink_restart_chn = 1;
}
/**
* @brief Request link switch done indication for TX channel
*/
static inline void axi_dma_ll_tx_request_link_switch_event(axi_dma_dev_t *dev, uint32_t channel)
{
switch (channel) {
case 0:
dev->link_switch_state.link_switch_state_ch0 = 1;
break;
case 1:
dev->link_switch_state.link_switch_state_ch1 = 1;
break;
case 2:
dev->link_switch_state.link_switch_state_ch2 = 1;
break;
default:
break;
}
}
/**
* @brief Check if TX link switch done indication is supported
*/
__attribute__((always_inline))
static inline bool axi_dma_ll_tx_is_link_switch_event_supported(axi_dma_dev_t *dev)
{
(void)dev;
return true;
}
/**
* @brief Check if DMA TX descriptor FSM is in IDLE state
*/
components/esp_hal_dma/esp32s31/include/hal/gdma_ll.h
+2 -3
View File
@@ -20,9 +20,8 @@
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
// the following event bits are only supported by axi-dma
#define GDMA_LL_EVENT_TX_LINK_SWITCH (1<<10)
// the following event bits are identical for ahb-dma, axi-dma and lp-ahb-dma
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
components/esp_hal_dma/gdma_hal_ahb_v1.c
+10 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,8 @@
static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
.m2m_free_periph_mask = GDMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = GDMA_LL_TX_EVENT_MASK,
.rx_event_mask = GDMA_LL_RX_EVENT_MASK,
};
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
@@ -182,6 +184,12 @@ void gdma_ahb_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_cha
}
#endif // SOC_GDMA_SUPPORT_ETM
bool gdma_ahb_hal_is_tx_link_switch_event_supported(gdma_hal_context_t *hal)
{
(void)hal;
return false;
}
void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
{
hal->dev = GDMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID);
@@ -206,5 +214,6 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
hal->set_burst_size = gdma_ahb_hal_set_burst_size;
#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
hal->is_tx_link_switch_event_supported = gdma_ahb_hal_is_tx_link_switch_event_supported;
hal->priv_data = &gdma_ahb_hal_priv_data;
}
components/esp_hal_dma/gdma_hal_ahb_v2.c
+12
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@@ -12,6 +12,8 @@
static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
.m2m_free_periph_mask = AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = AHB_DMA_LL_TX_EVENT_MASK,
.rx_event_mask = AHB_DMA_LL_RX_EVENT_MASK,
};
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
@@ -250,6 +252,12 @@ void gdma_ahb_hal_set_weight(gdma_hal_context_t *hal, int chan_id, gdma_channel_
}
#endif // SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
bool gdma_ahb_hal_is_tx_link_switch_event_supported(gdma_hal_context_t *hal)
{
(void)hal;
return false;
}
void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
{
hal->ahb_dma_dev = AHB_DMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID);
@@ -280,6 +288,7 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
hal->set_burst_size = gdma_ahb_hal_set_burst_size;
#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
hal->is_tx_link_switch_event_supported = gdma_ahb_hal_is_tx_link_switch_event_supported;
#if SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
hal->set_weight = gdma_ahb_hal_set_weight;
if (config->flags.enable_weighted_arbitration) {
@@ -304,6 +313,8 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
*/
static gdma_hal_priv_data_t gdma_lp_ahb_hal_priv_data = {
.m2m_free_periph_mask = LP_AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = AHB_DMA_LL_TX_EVENT_MASK,
.rx_event_mask = AHB_DMA_LL_RX_EVENT_MASK,
};
void gdma_lp_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
@@ -333,6 +344,7 @@ void gdma_lp_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *conf
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
hal->set_burst_size = gdma_ahb_hal_set_burst_size;
#endif // GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
hal->is_tx_link_switch_event_supported = gdma_ahb_hal_is_tx_link_switch_event_supported;
// LP AHB GDMA has a different memory range
lp_ahb_dma_ll_set_default_memory_range(hal->ahb_dma_dev);
}
components/esp_hal_dma/gdma_hal_axi.c
+21
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@@ -12,6 +12,8 @@
static gdma_hal_priv_data_t gdma_axi_hal_priv_data = {
.m2m_free_periph_mask = AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = AXI_DMA_LL_TX_EVENT_MASK,
.rx_event_mask = AXI_DMA_LL_RX_EVENT_MASK,
};
void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
@@ -170,6 +172,15 @@ uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd
}
}
#if AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT
void gdma_axi_hal_request_link_switch_event(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
if (dir == GDMA_CHANNEL_DIRECTION_TX) {
axi_dma_ll_tx_request_link_switch_event(hal->axi_dma_dev, chan_id);
}
}
#endif // AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT
#if SOC_GDMA_SUPPORT_CRC
void gdma_axi_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
@@ -237,6 +248,11 @@ void gdma_axi_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_cha
}
#endif // SOC_GDMA_SUPPORT_ETM
bool gdma_axi_hal_is_tx_link_switch_event_supported(gdma_hal_context_t *hal)
{
return axi_dma_ll_tx_is_link_switch_event_supported(hal->axi_dma_dev);
}
void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
{
hal->axi_dma_dev = AXI_DMA_LL_GET_HW(config->group_id - GDMA_LL_AXI_GROUP_START_ID);
@@ -265,5 +281,10 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if SOC_GDMA_SUPPORT_ETM
hal->enable_etm_task = gdma_axi_hal_enable_etm_task;
#endif // SOC_GDMA_SUPPORT_ETM
hal->is_tx_link_switch_event_supported = gdma_axi_hal_is_tx_link_switch_event_supported;
#if AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT
hal->request_link_switch_event = gdma_axi_hal_request_link_switch_event;
#endif // AXI_DMA_LL_SUPPORT_TX_LINK_SWITCH_EVENT
axi_dma_ll_set_default_memory_range(hal->axi_dma_dev);
}
components/esp_hal_dma/gdma_hal_top.c
+10
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@@ -125,3 +125,13 @@ void gdma_hal_set_weight(gdma_hal_context_t *hal, int chan_id, gdma_channel_dire
hal->set_weight(hal, chan_id, dir, weight);
}
#endif // SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
void gdma_hal_request_link_switch_event(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
{
hal->request_link_switch_event(hal, chan_id, dir);
}
bool gdma_hal_is_tx_link_switch_event_supported(gdma_hal_context_t *hal)
{
return hal->is_tx_link_switch_event_supported(hal);
}
components/esp_hal_dma/include/hal/gdma_hal.h
+10 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -52,9 +52,9 @@ typedef struct {
typedef struct {
// The bitmap of the IDs that can be used by M2M are different between AXI DMA and AHB DMA, so we need to save a copy for each of them
uint32_t m2m_free_periph_mask;
// TODO: we can add more private data here, e.g. the interrupt event mask of interest
// for now, the AXI DMA and AHB DMA are sharing the same interrupt mask, so we don't need to store it here
// If one day they become incompatible, we shall save a copy for each of them as a private data
// Supported interrupt events can vary across DMA instances (e.g. AHB vs AXI)
uint32_t tx_event_mask;
uint32_t rx_event_mask;
} gdma_hal_priv_data_t;
/**
@@ -102,6 +102,8 @@ struct gdma_hal_context_t {
#if SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
void (*set_weight)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t weight); /// Set the channel weight
#endif // SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
bool (*is_tx_link_switch_event_supported)(gdma_hal_context_t *hal); /// Check if TX link-switch interrupt is supported
void (*request_link_switch_event)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Raise the interrupt when tx link switch complete
};
void gdma_hal_deinit(gdma_hal_context_t *hal);
@@ -161,6 +163,10 @@ void gdma_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel
void gdma_hal_set_weight(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t weight);
#endif //SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
void gdma_hal_request_link_switch_event(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
bool gdma_hal_is_tx_link_switch_event_supported(gdma_hal_context_t *hal);
#ifdef __cplusplus
}
#endif
components/esp_hal_dma/include/hal/gdma_hal_ahb.h
-32
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@@ -12,38 +12,6 @@
extern "C" {
#endif
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr);
void gdma_ahb_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_ahb_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_ahb_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id);
void gdma_ahb_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id);
void gdma_ahb_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
void gdma_ahb_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz);
void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back, bool eof_till_popped);
void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis);
void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask);
uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw);
uint32_t gdma_ahb_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
uint32_t gdma_ahb_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);
void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config);
void gdma_lp_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config);
components/esp_hal_dma/include/hal/gdma_hal_axi.h
+1 -33
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,38 +12,6 @@
extern "C" {
#endif
void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr);
void gdma_axi_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_axi_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_axi_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_axi_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority);
void gdma_axi_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int periph_id);
void gdma_axi_hal_connect_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, int dummy_id);
void gdma_axi_hal_disconnect_all(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
void gdma_axi_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst);
void gdma_axi_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz);
void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back, bool eof_till_popped);
void gdma_axi_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis);
void gdma_axi_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask);
uint32_t gdma_axi_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw);
uint32_t gdma_axi_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);
void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config);
#ifdef __cplusplus