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fix(ulp): fix lp uart keep wakeup triggered

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This commit is contained in:
hebinglin
2026-06-08 19:49:42 +08:00
parent a0688c6e32
commit f088b73ea8
12 changed files with 80 additions and 25 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
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@@ -1682,3 +1682,7 @@ config SOC_LP_CORE_SUPPORT_ETM
config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
bool
default y
config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1
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@@ -673,3 +673,4 @@
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED (1) /*!< LP UART wakeup source is kept triggered */
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+4
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@@ -1431,6 +1431,10 @@ config SOC_LP_CORE_SUPPORT_ETM
bool
default y
config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
bool
default y
config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1
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@@ -588,6 +588,7 @@
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED (1) /*!< LP UART wakeup source is kept triggered */
/*------------------------------------- DEBUG CAPS -------------------------------------*/
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
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@@ -1986,3 +1986,7 @@ config SOC_LP_CORE_SUPPORT_LP_ADC
config SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS
bool
default y
config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+1
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@@ -769,3 +769,4 @@
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */
#define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED (1) /*!< LP UART wakeup source is kept triggered */
components/ulp/lp_core/lp_core/lp_core_utils.c
+17 -9
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@@ -25,9 +25,19 @@
#include "esp_cpu.h"
#include "ulp_lp_core_cpu_freq_shared.h"
#include "ulp_lp_core_lp_uart_shared.h"
#include "ulp_lp_core_uart.h"
static uint32_t lp_wakeup_cause = 0;
#if SOC_ULP_LP_UART_SUPPORTED
void ulp_lp_core_lp_uart_reset_wakeup_en(void)
{
lp_core_ll_enable_lp_uart_wakeup(false);
lp_core_ll_enable_lp_uart_wakeup(true);
}
#endif
void ulp_lp_core_update_wakeup_cause(void)
{
lp_wakeup_cause = 0;
@@ -42,6 +52,13 @@ void ulp_lp_core_update_wakeup_cause(void)
&& (uart_ll_get_intraw_mask(&LP_UART) & LP_UART_WAKEUP_INT_RAW)) {
lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_UART;
uart_ll_clr_intsts_mask(&LP_UART, LP_UART_WAKEUP_INT_CLR);
#if SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
// In these chips, the LP UART wakeup source is kept triggered, so we need to
// reset the wakeup register and flush the UART buffer manually after waking up.
lp_core_uart_tx_flush(LP_UART_NUM_0);
lp_core_uart_clear_buf();
ulp_lp_core_lp_uart_reset_wakeup_en();
#endif
}
#endif
@@ -133,15 +150,6 @@ void ulp_lp_core_delay_cycles(uint32_t cycles)
}
}
#if SOC_ULP_LP_UART_SUPPORTED
void ulp_lp_core_lp_uart_reset_wakeup_en(void)
{
lp_core_ll_enable_lp_uart_wakeup(false);
lp_core_ll_enable_lp_uart_wakeup(true);
}
#endif
void ulp_lp_core_halt(void)
{
lp_core_ll_request_sleep();
components/ulp/lp_core/shared/include/ulp_lp_core_lp_uart_shared.h
+5 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,9 +18,10 @@ extern "C" {
*
* @note This function configures the LP UART wakeup mode. Ensure that the UART has already been initialized
* with the lp_core_uart_init() call.
* Once the LP Core wakes up due to the LP UART, the wakeup feature is disabled.
* To re-enable the wakeup from the LP UART, you must call
* ulp_lp_core_lp_uart_reset_wakeup_en() again before the LP core goes to sleep.
* Once the LP Core wakes up due to the LP UART, the wakeup will be kept triggered in the chips with
* SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED. You need to call ulp_lp_core_lp_uart_reset_wakeup_en()
* to reset the wakeup signal and the UART buffer manually after waking up, which is done in ulp
* startup phase.
* Also be aware of limitations in different modes mentioned in the uart_wakeup_cfg_t struct.
*
*
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_uart_wakeup.c
+4 -6
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@@ -1,19 +1,17 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ulp_lp_core_utils.h"
#include "ulp_lp_core_print.h"
#include "ulp_lp_core_lp_uart_shared.h"
#include "lp_core_uart.h"
#include "ulp_lp_core_uart.h"
int main(void)
{
lp_core_printf("Hello world\r\n");
ulp_lp_core_delay_us(5000);
lp_core_uart_clear_buf();
ulp_lp_core_lp_uart_reset_wakeup_en();
lp_core_uart_tx_flush(LP_UART_NUM_0);
return 0;
}