diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h index a2fd9f5b4c4..78ffdaf35cf 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h @@ -310,6 +310,16 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable) { HP_SYS_CLKRST.ref_160m_ctrl0.reg_ref_160m_clk_en = enable; } + +/** + * Check if the clock gate for ref_160m is enabled + * @return true if enabled, false otherwise + */ +FORCE_INLINE_ATTR bool clk_gate_ll_ref_160m_clk_is_enabled(void) +{ + return HP_SYS_CLKRST.ref_160m_ctrl0.reg_ref_160m_clk_en; +} + /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define clk_gate_ll_ref_160m_clk_en(...) do { \ @@ -317,6 +327,39 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable) _clk_gate_ll_ref_160m_clk_en(__VA_ARGS__); \ } while(0) +/** + * Check if the clock gate for modem PLL is enabled + * @return true if enabled, false otherwise + */ +FORCE_INLINE_ATTR bool clk_gate_ll_modem_pll_clk_is_enabled(void) +{ + return HP_SYS_CLKRST.modem_conf.modem_pll_clk_en; +} + +/** + * Check if the clock gate for modem clock source is PLL + * @return true if PLL, false otherwise + */ +FORCE_INLINE_ATTR bool clk_gate_ll_modem_clk_source_is_pll(void) +{ + return HP_SYS_CLKRST.modem_conf.modem_clk_source_sel; +} + +/** + * Enable or disable the clock gate for modem PLL source + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_modem_pll_source_cg_en(bool enable) +{ + if (enable) { + HP_SYS_CLKRST.modem_conf.val = 0x15; + HP_SYS_CLKRST.modem_conf.val = 0x1d; + } else { + HP_SYS_CLKRST.modem_conf.val = 0x2d; + HP_SYS_CLKRST.modem_conf.val = 0x25; + } +} + /** * Enable or disable the clock gate for ref_240m (derived from BBPLL). * @param enable Enable / disable diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index c318e068bdc..2f164f45fe4 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -14,10 +14,10 @@ entries: esp_memory_utils (noflash) clk_utils (noflash) esp_clk_tree: esp_clk_tree_enable_src (noflash) + esp_clk_tree:esp_clk_tree_port_is_power_on (noflash) + esp_clk_tree_common:esp_clk_tree_is_power_on (noflash) if RTC_CLK_FUNC_IN_IRAM = y: esp_clk_tree:esp_clk_tree_enable_power (noflash) - esp_clk_tree:esp_clk_tree_port_is_power_on (noflash) - esp_clk_tree_common:esp_clk_tree_is_power_on (noflash) if SOC_CLK_MPLL_SUPPORTED = y: esp_clk_tree_common:esp_clk_tree_mpll_release (noflash) if SOC_CLK_APLL_SUPPORTED = y: diff --git a/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c index 96fb08fff3f..13c8c753411 100644 --- a/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c @@ -6,6 +6,7 @@ #include "esp_private/sleep_clock.h" #include "soc/hp_sys_clkrst_reg.h" +#include "soc/hp_alive_sys_reg.h" #include "soc/pmu_reg.h" #include "soc/lp_peri_clkrst_reg.h" #include "soc/ds_reg.h" @@ -16,30 +17,47 @@ ESP_LOG_ATTR_TAG(TAG, "sleep_clock"); +static esp_err_t sleep_clock_pll_source_retention_init(void *arg) +{ + /* Modem/system clock retention restore always powers BBPLL and runs calibration here. */ + const static sleep_retention_entries_config_t pll_source_regs_retention[] = { + /* Force BBPLL on (same effects as clk_ll_bbpll_enable) */ + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(0), PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C, PMU_TIE_HIGH_XPD_BBPLL_M | PMU_TIE_HIGH_XPD_BBPLL_I2C_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(1), PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(2), HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN, HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(3), PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_BBPLL_I2C | PMU_HP_ACTIVE_XPD_BBPLL, PMU_HP_ACTIVE_XPD_BBPLL_I2C_M | PMU_HP_ACTIVE_XPD_BBPLL_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + /* Enable i2c master clock */ + [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(4), LP_PERICLKRST_I2CMST_CTRL_REG, LP_PERICLKRST_LP_I2CMST_CLK_EN, LP_PERICLKRST_LP_I2CMST_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + /* Start SYSPLL self-calibration */ + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(5), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, 0, HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + /* Wait calibration done */ + [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PLL_LINK(6), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_BBPLL_CAL_END, HP_SYS_CLKRST_REG_BBPLL_CAL_END_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + /* Stop SYSPLL self-calibration */ + [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PLL_LINK(7), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_BBPLL_CAL_STOP, HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + }; + + esp_err_t err = sleep_retention_entries_create(pll_source_regs_retention, ARRAY_SIZE(pll_source_regs_retention), REGDMA_LINK_PRI_PLL_SOURCE, SLEEP_RETENTION_MODULE_PLL_SOURCE); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for PLL source retention"); + ESP_LOGI(TAG, "PLL source sleep retention initialization"); + return ESP_OK; +} + esp_err_t sleep_clock_system_retention_init(void *arg) { #define N_REGS_PCR() (((HP_SYS_CLKRST_CLK_EN0_REG - DR_REG_HP_SYS_CLKRST_BASE) / 4) + 1) const static sleep_retention_entries_config_t pcr_regs_retention[] = { - /* Enable i2c master clock */ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), LP_PERICLKRST_I2CMST_CTRL_REG, LP_PERICLKRST_LP_I2CMST_CLK_EN, LP_PERICLKRST_LP_I2CMST_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - /* Start SYSPLL self-calibration */ - [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, 0, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - /* Wait calibration done */ - [2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(2), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - /* Stop SYSPLL self-calibration */ - [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Clock configuration retention */ - [4] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0, + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR() - 1, 0, 0, 0xffbfffff, 0xffffffff, 0xffffffff, 0x7fffffff), .owner = ENTRY(0) | ENTRY(1)}, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(2), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [4] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(4), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* TOP PD wake: DS/ECDSA CLK_EN defaults to 1 and start mem clean; wait idle before restoring their clocks */ - [9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - [10] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(10), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, - [11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(11), HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_CRYPTO_CTRL0_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1)}, + [5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(5), DS_QUERY_BUSY_REG, 0, DS_QUERY_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), ECDSA_STATE_REG, 0, ECDSA_BUSY_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, + [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_CRYPTO_CTRL0_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1)}, }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); @@ -56,17 +74,16 @@ esp_err_t sleep_clock_modem_retention_init(void *arg) #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) #define N_REGS_LPCON() (((MODEM_LPCON_MODEM_INTR_STATUS_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) const static sleep_retention_entries_config_t modem_regs_retention[] = { - /* Workaround: on the restore path, issue a dummy write (value 0xf) to - * MODEM_SYSCON_DATE_REG (a benign date/version register) as the first - * REGDMA node to avoid an APB access timeout during the subsequent - * REGDMA operations. This is a hardware issue workaround; whether it - * can be removed on a future chip revision is still TODO/to be - * confirmed, so do not delete this node without verifying. */ - [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_DATE_REG, 0xf, 0xffffffff, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + /* !!! pll_source_regs_retention link above does not guarantee that the PMU has released the clock gate for the PLL. + * And due to hardware limitations, REGDMA is also unable to obtain the PMU's PLL gate status when the chip is in PD_TOP mode. + * So WORKAROUND with issue a dummy write to MODEM_SYSCON_DATE_REG as the first REGDMA node to avoid an APB access timeout + * during the subsequent REGDMA operations. */ + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_DATE_REG, MODEM_SYSCON_DATE, MODEM_SYSCON_DATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(0), HP_SYS_CLKRST_REF_160M_CTRL0_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN, HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M, 1, 0), .owner = ENTRY(1)}, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(1), HP_SYS_CLKRST_MODEM_CONF_REG, 0x3d, 0x3d, 1, 0), .owner = ENTRY(1)}, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(1), HP_SYS_CLKRST_MODEM_CONF_REG, 0x15, 0xff, 1, 0), .owner = ENTRY(1)}, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CLOCK_ICG_LINK(2), HP_SYS_CLKRST_MODEM_CONF_REG, 0x1d, 0xff, 1, 0), .owner = ENTRY(1)}, }; esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM); @@ -108,12 +125,14 @@ bool clock_domain_pd_allowed(void) sleep_retention_module_bitmap_t mask = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; const sleep_retention_module_bitmap_t system_modules = sleep_retention_module_bitmap_and(inited_modules, sys_clk_dep_modules); if (!sleep_retention_module_bitmap_eq(system_modules, null_module)) { + mask.bitmap[SLEEP_RETENTION_MODULE_PLL_SOURCE >> 5] |= BIT(SLEEP_RETENTION_MODULE_PLL_SOURCE % 32); mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_SYSTEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM % 32); } #if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED const sleep_retention_module_bitmap_t modem_modules = sleep_retention_module_bitmap_and(inited_modules, modem_clk_dep_modules); if (!sleep_retention_module_bitmap_eq(modem_modules, null_module)) { + mask.bitmap[SLEEP_RETENTION_MODULE_PLL_SOURCE >> 5] |= BIT(SLEEP_RETENTION_MODULE_PLL_SOURCE % 32); mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); } #endif @@ -129,7 +148,14 @@ bool clock_domain_pd_allowed(void) ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) { sleep_retention_module_init_param_t init_param = { + .cbs = { .create = { .handle = sleep_clock_pll_source_retention_init, .arg = NULL } }, + .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH + }; + sleep_retention_module_init(SLEEP_RETENTION_MODULE_PLL_SOURCE, &init_param); + + init_param = (sleep_retention_module_init_param_t) { .cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } }, + .depends = RETENTION_MODULE_BITMAP_INIT(PLL_SOURCE), .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH }; sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param); @@ -137,6 +163,7 @@ ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) #if CONFIG_MAC_BB_PD || CONFIG_BT_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE init_param = (sleep_retention_module_init_param_t) { .cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } }, + .depends = RETENTION_MODULE_BITMAP_INIT(PLL_SOURCE), .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE | SLEEP_RETENTION_MODULE_ATTR_ATTACH }; sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param); diff --git a/components/esp_hw_support/port/esp32s31/esp_clk_tree.c b/components/esp_hw_support/port/esp32s31/esp_clk_tree.c index 55893a72ed6..04c2c44c6d1 100644 --- a/components/esp_hw_support/port/esp32s31/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s31/esp_clk_tree.c @@ -243,68 +243,6 @@ static int16_t s_root_pll_power_ref_cnt[SOC_ROOT_CIRCUIT_CLK_MAX] = { 0 }; static bool s_clk_tree_initialized = false; -static int16_t esp_clk_tree_root_pll_power_acquire(soc_root_clk_circuit_t clk_circuit) -{ - int16_t prev; - - assert(clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL - || clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2); - - esp_os_enter_critical(&s_clk_tree_spinlock); - prev = s_root_pll_power_ref_cnt[clk_circuit]++; - if (prev == 0) { - switch (clk_circuit) { - case SOC_ROOT_CIRCUIT_CLK_BBPLL: - clk_ll_bbpll_enable(); - break; - case SOC_ROOT_CIRCUIT_CLK_CPLL: - clk_ll_cpll_enable(); - break; - case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: - clk_ll_xtalx2_enable(); - break; - default: - break; - } - } - esp_os_exit_critical(&s_clk_tree_spinlock); - return prev; -} - -static int16_t esp_clk_tree_root_pll_power_release(soc_root_clk_circuit_t clk_circuit) -{ - int16_t prev; - - assert(clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL - || clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2); - - esp_os_enter_critical(&s_clk_tree_spinlock); - prev = s_root_pll_power_ref_cnt[clk_circuit]; - if (prev <= 0) { - esp_os_exit_critical(&s_clk_tree_spinlock); - ESP_EARLY_LOGW(TAG, "soc_root_clk_circuit_t %d disabled multiple times!!", clk_circuit); - return prev; - } - s_root_pll_power_ref_cnt[clk_circuit] = prev - 1; - if (prev == 1) { - switch (clk_circuit) { - case SOC_ROOT_CIRCUIT_CLK_BBPLL: - clk_ll_bbpll_disable(); - break; - case SOC_ROOT_CIRCUIT_CLK_CPLL: - clk_ll_cpll_disable(); - break; - case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: - clk_ll_xtalx2_disable(); - break; - default: - break; - } - } - esp_os_exit_critical(&s_clk_tree_spinlock); - return prev; -} - static uint32_t esp_clk_tree_ref_500m_pll_get_freq_hz(uint32_t div_num) { uint32_t up_hz; @@ -476,25 +414,41 @@ void esp_clk_tree_initialize(void) bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable) { - if (clk_circuit >= SOC_ROOT_CIRCUIT_CLK_MAX) { + if (clk_circuit != SOC_ROOT_CIRCUIT_CLK_BBPLL + && clk_circuit != SOC_ROOT_CIRCUIT_CLK_CPLL + && clk_circuit != SOC_ROOT_CIRCUIT_CLK_XTAL_X2) { return false; } bool toggled = false; - switch (clk_circuit) { - case SOC_ROOT_CIRCUIT_CLK_CPLL: - case SOC_ROOT_CIRCUIT_CLK_BBPLL: - case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: { - if (enable) { - toggled = (esp_clk_tree_root_pll_power_acquire(clk_circuit) == 0); - } else { - toggled = (esp_clk_tree_root_pll_power_release(clk_circuit) == 1); + esp_os_enter_critical(&s_clk_tree_spinlock); + if (enable) { + s_root_pll_power_ref_cnt[clk_circuit]++; + } else if (s_root_pll_power_ref_cnt[clk_circuit] <= 0) { + esp_os_exit_critical(&s_clk_tree_spinlock); + ESP_EARLY_LOGW(TAG, "soc_root_clk_circuit_t %d disabled multiple times!!", clk_circuit); + return false; + } + if (s_root_pll_power_ref_cnt[clk_circuit] == 1) { + switch (clk_circuit) { + case SOC_ROOT_CIRCUIT_CLK_BBPLL: + enable ? clk_ll_bbpll_enable() : clk_ll_bbpll_disable(); + break; + case SOC_ROOT_CIRCUIT_CLK_CPLL: + enable ? clk_ll_cpll_enable() : clk_ll_cpll_disable(); + break; + case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + enable ? clk_ll_xtalx2_enable() : clk_ll_xtalx2_disable(); + break; + default: + break; } - break; + toggled = true; } - default: - break; + if (!enable) { + s_root_pll_power_ref_cnt[clk_circuit]--; } + esp_os_exit_critical(&s_clk_tree_spinlock); return toggled; } diff --git a/components/esp_hw_support/port/esp32s31/pmu_sleep.c b/components/esp_hw_support/port/esp32s31/pmu_sleep.c index 42c0398c089..ef496e02857 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32s31/pmu_sleep.c @@ -15,8 +15,11 @@ #include "soc/rtc.h" #include "soc/pmu_struct.h" #include "esp_private/esp_pmu.h" +#include "esp_private/esp_clk_tree_common.h" #include "pmu_param.h" +#include "hal/clk_gate_ll.h" #include "hal/clk_tree_hal.h" +#include "hal/clk_tree_ll.h" #include "hal/lp_aon_hal.h" #include "hal/efuse_ll.h" #include "hal/efuse_hal.h" @@ -403,6 +406,26 @@ bool pmu_sleep_finish(bool dslp) esp_psram_impl_exit_halfsleep_mode(); #endif #endif + const bool modem_pll_clk_enabled = clk_gate_ll_modem_pll_clk_is_enabled(); + assert(modem_pll_clk_enabled == clk_gate_ll_modem_clk_source_is_pll()); + if (!modem_pll_clk_enabled) { // wake up from non-modem clock retention + /* Workaround for issue WIFI-7620 + * The BA bitmap and start sequence number are updated in the read-only + * registers only after the PLL clock is available. */ + bool ref_160_enabled = clk_gate_ll_ref_160m_clk_is_enabled(); + if (!ref_160_enabled) { + _clk_gate_ll_ref_160m_clk_en(true); + } + _clk_gate_ll_modem_pll_source_cg_en(true); + _clk_gate_ll_modem_pll_source_cg_en(false); + if (!ref_160_enabled) { + _clk_gate_ll_ref_160m_clk_en(false); + } + + if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL)) { // clear align HW to clk_tree ref + clk_ll_bbpll_disable(); + } + } } #if !SOC_APM_SUPPORTED diff --git a/components/esp_rom/esp32s31/ld/esp32s31.rom.phy.ld b/components/esp_rom/esp32s31/ld/esp32s31.rom.phy.ld index edf044ac8c3..5ad1ddc0fc6 100644 --- a/components/esp_rom/esp32s31/ld/esp32s31.rom.phy.ld +++ b/components/esp_rom/esp32s31/ld/esp32s31.rom.phy.ld @@ -36,7 +36,7 @@ phy_set_chan_reg = 0x2f801228; phy_i2c_master_reset = 0x2f80122c; phy_chan14_mic_enable = 0x2f801230; phy_chan14_mic_cfg = 0x2f801234; -phy_set_most_tpw = 0x2f801238; +//phy_set_most_tpw = 0x2f801238; phy_get_most_tpw = 0x2f80123c; phy_tx_state_out = 0x2f801240; phy_ant_dft_cfg = 0x2f801244; diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index dda243ecef8..cce8a732859 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit dda243ecef8005c7499448569b3800ebe462fb2b +Subproject commit cce8a7328597181ae4e34962b93aae3b73508f33 diff --git a/components/hal/esp32s31/modem_clock_hal.c b/components/hal/esp32s31/modem_clock_hal.c index 381bbb95890..35fb54221e0 100644 --- a/components/hal/esp32s31/modem_clock_hal.c +++ b/components/hal/esp32s31/modem_clock_hal.c @@ -122,13 +122,19 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c void IRAM_ATTR modem_clock_hal_enable_soc_pll_source_cg(modem_clock_hal_context_t *hal, bool enable) { (void)hal; - HP_SYS_CLKRST.modem_conf.val = enable ? 0x3d : 0x25; + if (enable) { + HP_SYS_CLKRST.modem_conf.val = 0x15; + HP_SYS_CLKRST.modem_conf.val = 0x1d; + } else { + HP_SYS_CLKRST.modem_conf.val = 0x2d; + HP_SYS_CLKRST.modem_conf.val = 0x25; + } } bool IRAM_ATTR modem_clock_hal_soc_pll_source_cg_is_enabled(modem_clock_hal_context_t *hal) { (void)hal; - return (HP_SYS_CLKRST.modem_conf.val == 0x3d); + return (HP_SYS_CLKRST.modem_conf.val == 0x1d); } void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) diff --git a/components/soc/esp32s31/include/soc/retention_periph_defs.h b/components/soc/esp32s31/include/soc/retention_periph_defs.h index 411eba8ebb0..de5d8d5254d 100644 --- a/components/soc/esp32s31/include/soc/retention_periph_defs.h +++ b/components/soc/esp32s31/include/soc/retention_periph_defs.h @@ -15,76 +15,78 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = 1, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ + /* PLL source (I2C master clock + SYSPLL self-calibration) */ + SLEEP_RETENTION_MODULE_PLL_SOURCE = 2, /* clock module, which includes system and modem */ - SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 2, + SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 3, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 4, /* Timer Group by target*/ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG0_TIMER1 = 7, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 8, - SLEEP_RETENTION_MODULE_TG1_TIMER1 = 9, + SLEEP_RETENTION_MODULE_TG0_WDT = 5, + SLEEP_RETENTION_MODULE_TG1_WDT = 6, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_TIMER1 = 8, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 9, + SLEEP_RETENTION_MODULE_TG1_TIMER1 = 10, /* AHB_DMA by channel */ - SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 10, - SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 11, - SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 12, - SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 13, - SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 14, + SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 11, + SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 12, + SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 13, + SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 14, + SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 15, /* AXI_DMA by channel */ - SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 15, - SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 16, - SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 17, + SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 16, + SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 17, + SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 18, /* LP_AHB_DMA by channel */ - SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 18, - SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 19, + SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 19, + SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 20, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_UART0 = 20, - SLEEP_RETENTION_MODULE_UART1 = 21, - SLEEP_RETENTION_MODULE_UART2 = 22, - SLEEP_RETENTION_MODULE_UART3 = 23, - SLEEP_RETENTION_MODULE_RMT0 = 24, - SLEEP_RETENTION_MODULE_I2S0 = 25, - SLEEP_RETENTION_MODULE_I2S1 = 26, - SLEEP_RETENTION_MODULE_I2C0 = 27, - SLEEP_RETENTION_MODULE_I2C1 = 28, - SLEEP_RETENTION_MODULE_ETM0 = 29, - SLEEP_RETENTION_MODULE_TWAI0 = 30, - SLEEP_RETENTION_MODULE_TWAI1 = 31, - SLEEP_RETENTION_MODULE_PARLIO0 = 32, - SLEEP_RETENTION_MODULE_GPSPI2 = 33, - SLEEP_RETENTION_MODULE_GPSPI3 = 34, - SLEEP_RETENTION_MODULE_LEDC0 = 35, - SLEEP_RETENTION_MODULE_LEDC1 = 36, - SLEEP_RETENTION_MODULE_MCPWM0 = 37, - SLEEP_RETENTION_MODULE_MCPWM1 = 38, - SLEEP_RETENTION_MODULE_MCPWM2 = 39, - SLEEP_RETENTION_MODULE_MCPWM3 = 40, - SLEEP_RETENTION_MODULE_SDM0 = 41, - SLEEP_RETENTION_MODULE_LCDCAM = 42, - SLEEP_RETENTION_MODULE_JPEG = 43, - SLEEP_RETENTION_MODULE_DMA2D = 44, - SLEEP_RETENTION_MODULE_PPA = 45, + SLEEP_RETENTION_MODULE_UART0 = 21, + SLEEP_RETENTION_MODULE_UART1 = 22, + SLEEP_RETENTION_MODULE_UART2 = 23, + SLEEP_RETENTION_MODULE_UART3 = 24, + SLEEP_RETENTION_MODULE_RMT0 = 25, + SLEEP_RETENTION_MODULE_I2S0 = 26, + SLEEP_RETENTION_MODULE_I2S1 = 27, + SLEEP_RETENTION_MODULE_I2C0 = 28, + SLEEP_RETENTION_MODULE_I2C1 = 29, + SLEEP_RETENTION_MODULE_ETM0 = 30, + SLEEP_RETENTION_MODULE_TWAI0 = 31, + SLEEP_RETENTION_MODULE_TWAI1 = 32, + SLEEP_RETENTION_MODULE_PARLIO0 = 33, + SLEEP_RETENTION_MODULE_GPSPI2 = 34, + SLEEP_RETENTION_MODULE_GPSPI3 = 35, + SLEEP_RETENTION_MODULE_LEDC0 = 36, + SLEEP_RETENTION_MODULE_LEDC1 = 37, + SLEEP_RETENTION_MODULE_MCPWM0 = 38, + SLEEP_RETENTION_MODULE_MCPWM1 = 39, + SLEEP_RETENTION_MODULE_MCPWM2 = 40, + SLEEP_RETENTION_MODULE_MCPWM3 = 41, + SLEEP_RETENTION_MODULE_SDM0 = 42, + SLEEP_RETENTION_MODULE_LCDCAM = 43, + SLEEP_RETENTION_MODULE_JPEG = 44, + SLEEP_RETENTION_MODULE_DMA2D = 45, + SLEEP_RETENTION_MODULE_PPA = 46, /* Modem module, which includes WiFi, BLE and 802.15.4 */ - SLEEP_RETENTION_MODULE_WIFI_MAC = 46, - SLEEP_RETENTION_MODULE_WIFI_BB = 47, - SLEEP_RETENTION_MODULE_BLE_MAC = 48, - SLEEP_RETENTION_MODULE_BT_BB = 49, - SLEEP_RETENTION_MODULE_802154_MAC = 50, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 51, - SLEEP_RETENTION_MODULE_MODEM_PHY = 52, - SLEEP_RETENTION_MODULE_PHY_FE = 53, + SLEEP_RETENTION_MODULE_WIFI_MAC = 47, + SLEEP_RETENTION_MODULE_WIFI_BB = 48, + SLEEP_RETENTION_MODULE_BLE_MAC = 49, + SLEEP_RETENTION_MODULE_BT_BB = 50, + SLEEP_RETENTION_MODULE_802154_MAC = 51, + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 52, + SLEEP_RETENTION_MODULE_MODEM_PHY = 53, + SLEEP_RETENTION_MODULE_PHY_FE = 54, - SLEEP_RETENTION_MODULE_ASRC = 53, + SLEEP_RETENTION_MODULE_ASRC = 55, SLEEP_RETENTION_MODULE_MAX, } periph_retention_module_t; -#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) && ((m <= SLEEP_RETENTION_MODULE_PPA))) +#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_PLL_SOURCE) && ((m <= SLEEP_RETENTION_MODULE_PPA))) #ifdef __cplusplus } diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h index 9f7d5d53711..0f0cff3a264 100644 --- a/components/soc/include/soc/regdma.h +++ b/components/soc/include/soc/regdma.h @@ -37,6 +37,7 @@ extern "C" { #define REGDMA_MODEMLPCON_LINK(_pri) ((0x03 << 8) | _pri) #define REGDMA_PAU_LINK(_pri) ((0x04 << 8) | _pri) #define REGDMA_PVT_LINK(_pri) ((0x05 << 8) | _pri) +#define REGDMA_PLL_LINK(_pri) ((0x06 << 8) | _pri) #define REGDMA_CACHE_LINK(_pri) ((0x0c << 8) | _pri) #define REGDMA_INTMTX_LINK(_pri) ((0x0d << 8) | _pri) @@ -79,9 +80,10 @@ extern "C" { #define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri) -#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0 -#define REGDMA_LINK_PRI_MODEM_CLK REGDMA_LINK_PRI_1 -#define REGDMA_LINK_PRI_CLOCK_ICG REGDMA_LINK_PRI_1 +#define REGDMA_LINK_PRI_PLL_SOURCE REGDMA_LINK_PRI_0 +#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_1 +#define REGDMA_LINK_PRI_MODEM_CLK REGDMA_LINK_PRI_2 +#define REGDMA_LINK_PRI_CLOCK_ICG REGDMA_LINK_PRI_2 #define REGDMA_LINK_PRI_CRITICAL_TEE_APM REGDMA_LINK_PRI_2 #define REGDMA_LINK_PRI_WIFI_MAC_BB REGDMA_LINK_PRI_3 #define REGDMA_LINK_PRI_NON_CRITICAL_TEE_APM REGDMA_LINK_PRI_4