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Merge branch 'refactor/make_i2c_hal_independent' into 'master'

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refactor(i2c): Make i2c hal layer independent

See merge request espressif/esp-idf!41562
This commit is contained in:
C.S.M
2025-09-16 18:51:57 +08:00
parent 06f84d323d 5ce39e8878
commit f00755319a
58 changed files with 125 additions and 43 deletions
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components/soc/CMakeLists.txt
-4
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@@ -124,10 +124,6 @@ if(CONFIG_SOC_I2S_SUPPORTED)
list(APPEND srcs "${target_folder}/i2s_periph.c")
endif()
if(CONFIG_SOC_I2C_SUPPORTED)
list(APPEND srcs "${target_folder}/i2c_periph.c")
endif()
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "${target_folder}/i3c_master_periph.c")
endif()
components/soc/esp32/i2c_periph.c
-30
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@@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};
components/soc/esp32c2/i2c_periph.c
-22
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@@ -1,22 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
};
components/soc/esp32c3/i2c_periph.c
-22
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@@ -1,22 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
};
components/soc/esp32c5/i2c_periph.c
-73
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@@ -1,73 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
#define LP_I2C_MUX_FUNC (3)
static_assert(SOC_I2C_NUM == (SOC_HP_I2C_NUM + SOC_LP_I2C_NUM));
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
/* I2C_NUM_0*/
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
/* LP_I2C_NUM_0*/
{
.module_name = "LP_I2C0",
.sda_out_sig = 0,
.sda_in_sig = 0,
.scl_out_sig = 0,
.scl_in_sig = 0,
.iomux_func = LP_I2C_MUX_FUNC,
.irq = ETS_LP_I2C_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 18
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
};
components/soc/esp32c6/i2c_periph.c
-74
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@@ -1,74 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/regdma.h"
#include "soc/i2c_reg.h"
#define LP_I2C_MUX_FUNC (1)
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "LP_I2C0",
.sda_out_sig = 0,
.sda_in_sig = 0,
.scl_out_sig = 0,
.scl_in_sig = 0,
.iomux_func = LP_I2C_MUX_FUNC,
.irq = ETS_LP_I2C_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 18
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
};
components/soc/esp32c61/i2c_periph.c
-62
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@@ -1,62 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
/* I2C_NUM_0*/
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 18
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG, I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG, 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG, I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG, 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
};
components/soc/esp32h2/i2c_periph.c
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@@ -1,98 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/regdma.h"
#include "soc/i2c_reg.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 18
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
#define I2C1_RETENTION_REGS_CNT 18
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
{i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1},
};
components/soc/esp32h21/i2c_periph.c
-30
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@@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};
components/soc/esp32h4/i2c_periph.c
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@@ -1,98 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/regdma.h"
#include "soc/i2c_reg.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 18
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
#define I2C1_RETENTION_REGS_CNT 18
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
{i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1},
};
components/soc/esp32p4/i2c_periph.c
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@@ -1,105 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/lp_gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2C0_SDA_PAD_OUT_IDX,
.sda_in_sig = I2C0_SDA_PAD_IN_IDX,
.scl_out_sig = I2C0_SCL_PAD_OUT_IDX,
.scl_in_sig = I2C0_SCL_PAD_IN_IDX,
.irq = ETS_I2C0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2C1_SDA_PAD_OUT_IDX,
.sda_in_sig = I2C1_SDA_PAD_IN_IDX,
.scl_out_sig = I2C1_SCL_PAD_OUT_IDX,
.scl_in_sig = I2C1_SCL_PAD_IN_IDX,
.irq = ETS_I2C1_INTR_SOURCE,
},
{
.module_name = "LP_I2C0",
.sda_out_sig = LP_I2C_SDA_PAD_OUT_IDX,
.sda_in_sig = LP_I2C_SDA_PAD_IN_IDX,
.scl_out_sig = LP_I2C_SCL_PAD_OUT_IDX,
.scl_in_sig = LP_I2C_SCL_PAD_IN_IDX,
.irq = ETS_LP_I2C_INTR_SOURCE,
},
};
// I2C sleep retention entries
// I2C registers require set the reg_update bit to make the configuration take effect
/* I2C Registers Context
Include: I2C_SCL_LOW_PERIOD_REG /
I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
*/
#define I2C0_RETENTION_REGS_CNT 18
#define I2C0_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(0)
static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c0_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
.owner = ENTRY(0)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0)
}, \
};
#define I2C1_RETENTION_REGS_CNT 18
#define I2C1_RETENTION_MAP_BASE I2C_SCL_LOW_PERIOD_REG(1)
static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
static const regdma_entries_config_t i2c1_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
.owner = ENTRY(0)
}, \
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0)
}, \
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \
.owner = ENTRY(0)
}, \
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0)
}, \
[4] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
.owner = ENTRY(0)
}, \
};
const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
{i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
{i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1},
};
components/soc/esp32s2/i2c_periph.c
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@@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};
components/soc/esp32s3/i2c_periph.c
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@@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.module_name = "I2C0",
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
},
{
.module_name = "I2C1",
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
.irq = ETS_I2C_EXT1_INTR_SOURCE,
},
};
components/soc/include/soc/i2c_periph.h
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@@ -1,47 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/i2c_reg.h"
#include "soc/i2c_struct.h"
#include "soc/soc_caps.h"
#if SOC_I2C_SUPPORTED
#include "soc/regdma.h"
#include "soc/interrupts.h"
#if SOC_I2C_SUPPORT_SLEEP_RETENTION
#include "soc/retention_periph_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
const char *module_name;
const uint8_t sda_out_sig;
const uint8_t sda_in_sig;
const uint8_t scl_out_sig;
const uint8_t scl_in_sig;
const uint8_t iomux_func;
const uint8_t irq;
} i2c_signal_conn_t;
extern const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM];
#if SOC_I2C_SUPPORT_SLEEP_RETENTION
typedef struct {
const regdma_entries_config_t *link_list;
uint32_t link_num;
periph_retention_module_t module_id;
} i2c_reg_ctx_link_t;
extern const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM];
#endif
#ifdef __cplusplus
}
#endif
#endif // SOC_I2C_SUPPORTED