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Merge branch 'release/v6.0' into 'feat/mcpwm_support_h4_v6.0'

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# Conflicts:
#   docs/docs_not_updated/esp32h4.txt
This commit is contained in:
Chen Chen
2025-11-19 17:14:21 +08:00
parent cb48f80f52 771edaec0c
commit efbddafbf0
696 changed files with 16351 additions and 19318 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/CMakeLists.txt
-8
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@@ -84,10 +84,6 @@ if(CONFIG_SOC_EMAC_SUPPORTED)
list(APPEND srcs "${target_folder}/emac_periph.c")
endif()
if(CONFIG_SOC_ETM_SUPPORTED)
list(APPEND srcs "${target_folder}/etm_periph.c")
endif()
if(CONFIG_SOC_GPSPI_SUPPORTED)
list(APPEND srcs "${target_folder}/spi_periph.c")
endif()
@@ -154,10 +150,6 @@ if(CONFIG_SOC_IEEE802154_SUPPORTED)
endif()
endif()
if(CONFIG_SOC_USB_OTG_SUPPORTED)
list(APPEND srcs "${target_folder}/usb_dwc_periph.c")
endif()
if(CONFIG_SOC_DAC_SUPPORTED)
list(APPEND srcs "${target_folder}/dac_periph.c")
endif()
components/soc/esp32/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -355,10 +355,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32/include/soc/soc_caps.h
-3
View File
@@ -199,9 +199,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32 has 2 I2C
#define SOC_I2C_NUM (2U)
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -323,10 +323,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 1
components/soc/esp32c2/include/soc/soc_caps.h
-3
View File
@@ -149,9 +149,6 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C2 has 1 I2C
#define SOC_I2C_NUM (1U)
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -419,10 +419,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 1
components/soc/esp32c3/include/soc/soc_caps.h
-3
View File
@@ -188,9 +188,6 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 has 1 I2C
#define SOC_I2C_NUM (1U)
components/soc/esp32c5/etm_periph.c
-44
View File
@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+8 -4
View File
@@ -519,6 +519,10 @@ config SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
bool
default y
config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
int
default 16
config SOC_GPIO_PORT
int
default 1
@@ -579,10 +583,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
@@ -1003,6 +1003,10 @@ config SOC_ECC_CONSTANT_TIME_POINT_MUL
bool
default y
config SOC_ECC_SUPPORT_CURVE_P384
bool
default y
config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+2 -2
View File
@@ -203,6 +203,7 @@
#define SOC_GDMA_SUPPORT_ETM 1
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION 1
#define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT (16)
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C5 has 1 GPIO peripheral
@@ -237,8 +238,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
@@ -411,6 +410,7 @@
/*--------------------------- ECC CAPS ---------------------------------------*/
#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1
#define SOC_ECC_SUPPORT_CURVE_P384 (1)
/*--------------------------- ECDSA CAPS ---------------------------------------*/
#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
components/soc/esp32c5/include/soc/soc_caps_full.h
-4
View File
@@ -23,10 +23,6 @@
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32c6/etm_periph.c
-44
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@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -511,10 +511,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
-2
View File
@@ -215,8 +215,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32c6/include/soc/soc_caps_full.h
-4
View File
@@ -23,10 +23,6 @@
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32c61/etm_periph.c
-44
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@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+4 -4
View File
@@ -395,6 +395,10 @@ config SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION
bool
default y
config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
int
default 16
config SOC_ETM_SUPPORT_SLEEP_RETENTION
bool
default y
@@ -455,10 +459,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+1 -2
View File
@@ -159,6 +159,7 @@
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION 1
#define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT (16)
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
@@ -196,8 +197,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32c61/include/soc/soc_caps_full.h
-4
View File
@@ -13,10 +13,6 @@
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*--------------------------- I2S CAPS ----------------------------------------*/
// helper macros to access module attributes
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h2/etm_periph.c
-44
View File
@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -531,10 +531,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
-2
View File
@@ -240,8 +240,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32h2/include/soc/soc_caps_full.h
-4
View File
@@ -23,10 +23,6 @@
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -387,10 +387,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
-2
View File
@@ -220,8 +220,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
components/soc/esp32h21/include/soc/soc_caps_full.h
-4
View File
@@ -19,10 +19,6 @@
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
// #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h4/etm_periph.c
-44
View File
@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/soc/esp32h4/include/soc/soc_caps_full.h
-4
View File
@@ -19,10 +19,6 @@
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h4/usb_dwc_periph.c
-48
View File
@@ -1,48 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/gpio_sig_map.h"
#include "soc/interrupts.h"
#include "soc/usb_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_OUT_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_OUT_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_OUT_IDX,
.drvvbus = USB_OTG_DRVVBUS_OUT_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_OUT_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_OUT_IDX,
};
static const usb_internal_phy_io_t internal_phy_io = {
.dp = 21,
.dm = 22,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = NULL,
.otg_signals = &otg_signals,
.internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_OTG11_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
components/soc/esp32p4/etm_periph.c
-44
View File
@@ -1,44 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+21 -5
View File
@@ -627,7 +627,7 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
int
default 16
@@ -695,6 +695,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x007FFFFFFFFF0000
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
@@ -715,10 +723,6 @@ config SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH
int
default 16
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 16
@@ -919,6 +923,10 @@ config SOC_ISP_SHARPEN_SUPPORTED
bool
default y
config SOC_ISP_WBG_SUPPORTED
bool
default y
config SOC_ISP_SHARE_CSI_BRG
bool
default y
@@ -1371,6 +1379,14 @@ config SOC_SHA_SUPPORT_SHA512_T
bool
default y
config SOC_ECC_CONSTANT_TIME_POINT_MUL
bool
default y
config SOC_ECC_SUPPORT_CURVE_P384
bool
default y
config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+11 -4
View File
@@ -230,7 +230,7 @@
#define SOC_GDMA_SUPPORT_CRC 1
#define SOC_GDMA_SUPPORT_ETM 1
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT (16)
#define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT (16)
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-P4 has 1 GPIO peripheral
@@ -265,6 +265,11 @@
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) // Supported only on ESP32P4 rev >= 3.0 (see DIG-399)
// The Clock Out signal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (2)
@@ -273,9 +278,6 @@
#define SOC_DEBUG_PROBE_NUM_UNIT (1U) // Number of debug probe units
#define SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH (16) // Maximum width of the debug probe output in each unit
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 16
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
@@ -353,6 +355,7 @@
#define SOC_ISP_DVP_SUPPORTED 1
#define SOC_ISP_LSC_SUPPORTED 1
#define SOC_ISP_SHARPEN_SUPPORTED 1
#define SOC_ISP_WBG_SUPPORTED 1
#define SOC_ISP_SHARE_CSI_BRG 1
#define SOC_ISP_NUMS 1U
@@ -518,6 +521,10 @@
#define SOC_SHA_SUPPORT_SHA512_256 (1)
#define SOC_SHA_SUPPORT_SHA512_T (1)
/*--------------------------- ECC CAPS ---------------------------------------*/
#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1
#define SOC_ECC_SUPPORT_CURVE_P384 (1)
/*--------------------------- ECDSA CAPS ---------------------------------------*/
#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1)
components/soc/esp32p4/include/soc/soc_caps_full.h
-4
View File
@@ -23,10 +23,6 @@
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define _SOC_CAPS_I2S_INST_NUM 3 // Number of I2S instances
components/soc/esp32p4/include/soc/system_periph_retention.h
+1 -1
View File
@@ -32,7 +32,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define CACHE_RETENTION_LINK_LEN 10
#define CACHE_RETENTION_LINK_LEN 12
extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN];
/**
components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
+1 -33
View File
@@ -413,37 +413,6 @@ typedef union {
} hp_crypto_ctrl_reg_t;
/** Group: HP GPIO O HOLD CTRL0 REG */
/** Type of gpio_o_hold_ctrl0 register
* NA
*/
typedef union {
struct {
/** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
* hold control for gpio47~16
*/
uint32_t reg_gpio_0_hold_low:32;
};
uint32_t val;
} hp_gpio_o_hold_ctrl0_reg_t;
/** Group: HP GPIO O HOLD CTRL1 REG */
/** Type of gpio_o_hold_ctrl1 register
* NA
*/
typedef union {
struct {
/** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
* hold control for gpio56~48
*/
uint32_t reg_gpio_0_hold_high:9;
uint32_t reserved_9:23;
};
uint32_t val;
} hp_gpio_o_hold_ctrl1_reg_t;
/** Group: HP SYS RDN ECO CS REG */
/** Type of sys_rdn_eco_cs register
* NA
@@ -2149,8 +2118,7 @@ typedef struct hp_system_dev_t {
volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st;
uint32_t reserved_068[2];
volatile hp_crypto_ctrl_reg_t crypto_ctrl;
volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
uint32_t reserved_074[2];
volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs;
volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en;
volatile hp_l2_mem_subsize_reg_t l2_mem_subsize;
components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
+1 -17
View File
@@ -114,22 +114,6 @@ typedef union {
} lp_iomux_ext_wakeup0_sel_reg_t;
/** Group: lp_pad_hold */
/** Type of lp_pad_hold register
* Reserved
*/
typedef union {
struct {
/** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
* Reserved
*/
uint32_t reg_lp_gpio_hold:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_iomux_lp_pad_hold_reg_t;
/** Group: lp_pad_hys */
/** Type of lp_pad_hys register
* Reserved
@@ -151,7 +135,7 @@ typedef struct lp_iomux_dev_t {
volatile lp_iomux_ver_date_reg_t ver_date;
volatile lp_iomux_pad_reg_t pad[16];
volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
uint32_t reserved_04c;
volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
} lp_iomux_dev_t;
components/soc/esp32p4/register/hw_ver3/soc/lp_system_reg.h
+17 -2
View File
@@ -1083,7 +1083,15 @@ extern "C" {
* need_des
*/
#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
/** LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE : R/W; bitpos: [2:0]; default: 0;
* need_des
*/
#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE 0x7U
#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_M (LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_V << LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_S)
#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_V 0x7U
#define LP_SYSTEM_REG_HP_MEM_LOWPOWER_MODE_S 0
/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:3]; default: 1038;
* need_des
*/
#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL 0xFFFFFFFFU
@@ -1095,7 +1103,14 @@ extern "C" {
* need_des
*/
#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
/** LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE : R/W; bitpos: [2:0]; default: 0;
* need_des
*/
#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE 0x7U
#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_M (LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_V << LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_S)
#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_V 0x7U
#define LP_SYSTEM_REG_LP_MEM_LOWPOWER_MODE_S 0
/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:3]; default: 1038;
* need_des
*/
#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL 0xFFFFFFFFU
components/soc/esp32p4/register/hw_ver3/soc/lp_system_struct.h
+12 -4
View File
@@ -768,10 +768,14 @@ typedef union {
*/
typedef union {
struct {
/** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
/** hp_mem_lowpower_mode : R/W; bitpos: [2:0]; default: 0;
* need_des
*/
uint32_t hp_mem_aux_ctrl:32;
uint32_t hp_mem_lowpower_mode:3;
/** hp_mem_aux_ctrl : R/W; bitpos: [31:3]; default: 1038;
* need_des
*/
uint32_t hp_mem_aux_ctrl:29;
};
uint32_t val;
} lp_system_reg_hp_mem_aux_ctrl_reg_t;
@@ -781,10 +785,14 @@ typedef union {
*/
typedef union {
struct {
/** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
/** lp_mem_lowpower_mode : R/W; bitpos: [2:0]; default: 0;
* need_des
*/
uint32_t lp_mem_aux_ctrl:32;
uint32_t lp_mem_lowpower_mode:3;
/** lp_mem_aux_ctrl : R/W; bitpos: [31:3]; default: 1038;
* need_des
*/
uint32_t lp_mem_aux_ctrl:29;
};
uint32_t val;
} lp_system_reg_lp_mem_aux_ctrl_reg_t;
components/soc/esp32p4/system_retention_periph.c
+31 -21
View File
@@ -45,17 +45,23 @@ static const uint32_t l1_cache_regs_map[4] = {0x7, 0x0, 0xc000000, 0x0};
CACHE_L2_CACHE_ACS_FAIL_CTRL_REG & CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG */
#define L2_CACHE_RETENTION_REGS_CNT (6)
#define L2_CACHE_RETENTION_REGS_BASE (CACHE_L2_CACHE_CTRL_REG)
#define L1_CACHE_ACS_FAIL_INR_CLR (CACHE_L1_ICACHE0_FAIL_INT_CLR | CACHE_L1_ICACHE1_FAIL_INT_CLR | CACHE_L1_ICACHE2_FAIL_INT_CLR | CACHE_L1_ICACHE3_FAIL_INT_CLR |CACHE_L1_DCACHE_FAIL_INT_CLR)
#define L1_CACHE_ACS_FAIL_INR_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_M | CACHE_L1_ICACHE1_FAIL_INT_CLR_M | CACHE_L1_ICACHE2_FAIL_INT_CLR_M | CACHE_L1_ICACHE3_FAIL_INT_CLR_M |CACHE_L1_DCACHE_FAIL_INT_CLR_M)
static const uint32_t l2_cache_regs_map[4] = {0xc000000f, 0x0, 0x0, 0x0};
const regdma_entries_config_t cache_regs_retention[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x00), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \
// Clear the cache error status, since the auto clock gating added to the cache after version v3, it may falsely report cache acs fail when the module is reset.
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x00), CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, L1_CACHE_ACS_FAIL_INR_CLR, L1_CACHE_ACS_FAIL_INR_CLR_M, 1, 0), .owner = ENTRY(0) },
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x01), CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG, CACHE_L2_CACHE_FAIL_INT_CLR, CACHE_L2_CACHE_FAIL_INT_CLR_M, 1, 0), .owner = ENTRY(0) },
[2] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x02), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \
L1_CACHE_RETENTION_REGS_CNT, 0, 0, \
l1_cache_regs_map[0], l1_cache_regs_map[1], \
l1_cache_regs_map[2], l1_cache_regs_map[3]), \
.owner = ENTRY(0)
},
[1] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x01), \
[3] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x03), \
L2_CACHE_RETENTION_REGS_BASE, L2_CACHE_RETENTION_REGS_BASE, \
L2_CACHE_RETENTION_REGS_CNT, 0, 0, \
l2_cache_regs_map[0], l2_cache_regs_map[1], \
@@ -63,15 +69,15 @@ const regdma_entries_config_t cache_regs_retention[] = {
.owner = ENTRY(0)
},
// Invalidate L1 Cache
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x02), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x03), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) },
[8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
[9] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x09), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) },
// Reset L2 CACHE SYNC
[8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x09), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
[10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x10), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
[11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x11), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
};
_Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");
@@ -127,19 +133,23 @@ _Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "In
#define N_REGS_SPI0_C_MEM_1() (((SPI_MEM_C_SMEM_AC_REG - SPI_MEM_C_FMEM__PMS0_ATTR_REG) / 4) + 1)
#define N_REGS_SPI0_C_MEM_2() (1)
#define N_REGS_SPI0_C_MEM_3() (((SPI_MEM_C_DPA_CTRL_REG - SPI_MEM_C_MMU_POWER_CTRL_REG) / 4) + 1)
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define FLASH_SPIMEM_RETENTION_ENTRY (ENTRY(0) | REGDMA_SW_TRIGGER_ENTRY)
#else
#define FLASH_SPIMEM_RETENTION_ENTRY ENTRY(0)
#endif
const regdma_entries_config_t flash_spimem_regs_retention[] = {
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE, DR_REG_FLASH_SPI1_BASE, N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = ENTRY(0) }, /* spi1_mem */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG, SPI1_MEM_C_INT_ENA_REG, N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = ENTRY(0) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_C_TIMING_CALI_REG, SPI1_MEM_C_TIMING_CALI_REG, N_REGS_SPI1_C_MEM_2(), 0, 0), .owner = ENTRY(0) },
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE, DR_REG_FLASH_SPI1_BASE, N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* spi1_mem */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG, SPI1_MEM_C_INT_ENA_REG, N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_C_TIMING_CALI_REG, SPI1_MEM_C_TIMING_CALI_REG, N_REGS_SPI1_C_MEM_2(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), DR_REG_FLASH_SPI0_BASE, DR_REG_FLASH_SPI0_BASE, N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = ENTRY(0) }, /* spi0_mem */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG, SPI_MEM_C_FMEM__PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), DR_REG_FLASH_SPI0_BASE, DR_REG_FLASH_SPI0_BASE, N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY }, /* spi0_mem */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_FMEM__PMS0_ATTR_REG, SPI_MEM_C_FMEM__PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x08), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = FLASH_SPIMEM_RETENTION_ENTRY },
};
_Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions");
components/soc/esp32p4/usb_dwc_periph.c
-59
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@@ -1,59 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/interrupts.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/usb_dwc_struct.h"
/* -------------------------------- Private --------------------------------- */
static const usb_otg_signal_conn_t dwc_fs_otg_signals = {
// Inputs
.iddig = USB_OTG11_IDDIG_PAD_IN_IDX,
.avalid = USB_OTG11_AVALID_PAD_IN_IDX,
.bvalid = USB_SRP_BVALID_PAD_IN_IDX,
.vbusvalid = USB_OTG11_VBUSVALID_PAD_IN_IDX,
.sessend = USB_SRP_SESSEND_PAD_IN_IDX,
// Outputs
.idpullup = USB_OTG11_IDPULLUP_PAD_OUT_IDX,
.dppulldown = USB_OTG11_DPPULLDOWN_PAD_OUT_IDX,
.dmpulldown = USB_OTG11_DMPULLDOWN_PAD_OUT_IDX,
.drvvbus = USB_OTG11_DRVVBUS_PAD_OUT_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_PAD_OUT_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_PAD_OUT_IDX,
};
static const usb_internal_phy_io_t internal_phy_io = {
.dp = 27,
.dm = 26,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
// High-Speed USB-DWC
[0] = {
.fsls_signals = NULL,
.otg_signals = NULL,
.internal_phy_io = NULL, // HS PHY is not mapped to any GPIO
.supported_phys = USB_PHY_INST_UTMI_0,
.irq = ETS_USB_OTG_INTR_SOURCE,
.irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
},
// Full-Speed USB-DWC
[1] = {
.fsls_signals = NULL,
.otg_signals = &dwc_fs_otg_signals,
.internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_OTG11_CH0_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
-4
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@@ -415,10 +415,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_HAS_INTERRUPT
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
-3
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@@ -190,9 +190,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
components/soc/esp32s2/usb_dwc_periph.c
-60
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@@ -1,60 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_sig_map.h"
#include "soc/interrupts.h"
#include "soc/usb_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_fsls_serial_signal_conn_t fsls_signals = {
// Inputs
.rx_dp = USB_EXTPHY_VP_IDX,
.rx_dm = USB_EXTPHY_VM_IDX,
.rx_rcv = USB_EXTPHY_RCV_IDX,
// Outputs
.suspend_n = USB_EXTPHY_SUSPND_IDX,
.tx_enable_n = USB_EXTPHY_OEN_IDX,
.tx_dp = USB_EXTPHY_VPO_IDX,
.tx_dm = USB_EXTPHY_VMO_IDX,
.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
};
static const usb_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
.drvvbus = USB_OTG_DRVVBUS_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
};
static const usb_internal_phy_io_t internal_phy_io = {
.dp = 20,
.dm = 19,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = &fsls_signals,
.otg_signals = &otg_signals,
.internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -479,10 +479,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32s3/include/soc/soc_caps.h
-3
View File
@@ -201,9 +201,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S3 has 2 I2C
#define SOC_I2C_NUM (2U)
components/soc/esp32s3/usb_dwc_periph.c
-60
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@@ -1,60 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_sig_map.h"
#include "soc/interrupts.h"
#include "soc/usb_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_fsls_serial_signal_conn_t fsls_signals = {
// Inputs
.rx_dp = USB_EXTPHY_VP_IDX,
.rx_dm = USB_EXTPHY_VM_IDX,
.rx_rcv = USB_EXTPHY_RCV_IDX,
// Outputs
.suspend_n = USB_EXTPHY_SUSPND_IDX,
.tx_enable_n = USB_EXTPHY_OEN_IDX,
.tx_dp = USB_EXTPHY_VPO_IDX,
.tx_dm = USB_EXTPHY_VMO_IDX,
.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
};
static const usb_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
.drvvbus = USB_OTG_DRVVBUS_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
};
static const usb_internal_phy_io_t internal_phy_io = {
.dp = 20,
.dm = 19,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = &fsls_signals,
.otg_signals = &otg_signals,
.internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
components/soc/include/soc/etm_periph.h
-38
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@@ -1,38 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps_full.h"
#include "soc/regdma.h"
#if SOC_HAS(PAU)
#include "soc/retention_periph_defs.h"
#endif
// helper macros to access module attributes
#define SOC_ETM_ATTR(_attr) SOC_MODULE_ATTR(ETM, _attr)
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_HAS(PAU)
typedef struct {
periph_retention_module_t module; // ID of the ETM as a retention module
const regdma_entries_config_t *regdma_entry_array; // Array of regdma entries for retention
uint32_t array_size; // Size of the regdma_entry_array
} soc_etm_retention_desc_t;
extern const soc_etm_retention_desc_t soc_etm_retention_info[SOC_ETM_ATTR(INST_NUM)];
#endif // SOC_HAS(PAU)
#ifdef __cplusplus
}
#endif
components/soc/include/soc/usb_periph.h
-112
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@@ -1,112 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_pins.h"
#include "soc/soc_caps.h"
#include "soc/gpio_sig_map.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_OTG_SUPPORTED
/* ---------------------------------- Types --------------------------------- */
/**
* @brief USB PHY Instance Type
*/
typedef enum {
USB_PHY_INST_FSLS_INTERN_0 = (1 << 0),
USB_PHY_INST_FSLS_INTERN_1 = (1 << 1),
USB_PHY_INST_UTMI_0 = (1 << 2),
USB_PHY_INST_EXTERN = (1 << 3),
} usb_phy_inst_t;
/**
* @brief USB PHY FSLS Serial Interface Signals
*
* Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial
* interface's signals.
*
* @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more
* details regarding the FSLS Serial Interface.
*/
typedef struct {
// Inputs
int rx_dp;
int rx_dm;
int rx_rcv;
// Outputs
int suspend_n;
int tx_enable_n;
int tx_dp;
int tx_dm;
int fs_edge_sel;
} usb_fsls_serial_signal_conn_t;
/**
* @brief USB PHY UTMI OTG Interface Signal Index Type
*
* Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's
* OTG signals.
*/
typedef struct {
// Inputs
int iddig;
int avalid;
int bvalid;
int vbusvalid;
int sessend;
// Outputs
int idpullup;
int dppulldown;
int dmpulldown;
int drvvbus;
int chrgvbus;
int dischrgvbus;
} usb_otg_signal_conn_t;
/**
* @brief Internal USB PHY IO
*
* Structure to store the IO numbers for a particular internal USB PHY
*/
typedef struct {
int dp;
int dm;
} usb_internal_phy_io_t;
/**
* @brief USB Controller Information
*
* Structure to store information for all USB-DWC instances
*
* For targets with multiple USB controllers, we support only fixed mapping of the PHYs.
* This is a software limitation; the hardware supports swapping Controllers and PHYs.
*/
typedef struct {
struct {
const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller
const usb_otg_signal_conn_t * const otg_signals;
const usb_internal_phy_io_t * const internal_phy_io; // Must be set for internal FSLS PHY(s)
const usb_phy_inst_t supported_phys; // Bitmap of supported PHYs by this controller
const int irq;
const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
} controllers [SOC_USB_OTG_PERIPH_NUM];
} usb_dwc_info_t;
extern const usb_dwc_info_t usb_dwc_info;
#endif // SOC_USB_OTG_SUPPORTED
#ifdef __cplusplus
}
#endif