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refactor(lcdcam): move shared core clock setup to drivers

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Configure the shared LCDCAM core clock through guarded LCD and CAM LL APIs,
and unify LCD functional clock LL calls around group IDs across supported targets.

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
morris
2026-09-08 14:47:41 +08:00
co-authored by Cursor
parent 1fd26d0846
commit ef6b7b742f
9 changed files with 183 additions and 52 deletions
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components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h
-8
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@@ -149,14 +149,6 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_t0_clk_en = 0;
HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_t1_clk_en = 0;
HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_wdt_clk_en = 0;
// LCDCAM
/*
* Default lcdcam_lcdcam_ctrl0:
* reg_lcdcam_clk_src_sel: 1 (BBPLL 120 MHz path, shared by LCD and CAM)
* reg_lcdcam_clk_div_num: 1 (divide by 2 → 60 MHz)
*/
HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 1;
HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_div_num = 1;
// ASRC
HP_SYS_CLKRST.ahb_asrc_ctrl0.reg_ahb_asrc_sys_clk_en = 0;
// Flash