From ee9d199d7f63ef0265542199506511c2a23151f9 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Mon, 13 Apr 2026 15:21:44 +0200 Subject: [PATCH] fix(lp_core): skip LP UART RTS/CTS pin setup when flow control is disabled lp_core_uart_set_pin() unconditionally configured the RTS and CTS GPIO pins even when flow control was disabled. Only configure the RTS pin when UART_HW_FLOWCTRL_RTS is set, and the CTS pin when UART_HW_FLOWCTRL_CTS is set. --- components/ulp/lp_core/lp_core_uart.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c index 322ef7ff8af..0c84c525a13 100644 --- a/components/ulp/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core_uart.c @@ -154,10 +154,13 @@ static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg) ret = lp_uart_config_io(cfg->uart_pin_cfg.tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_TX_PIN_IDX); /* Configure Rx Pin */ ret = lp_uart_config_io(cfg->uart_pin_cfg.rx_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_RX_PIN_IDX); - /* Configure RTS Pin */ - ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_RTS_PIN_IDX); - /* Configure CTS Pin */ - ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_CTS_PIN_IDX); + /* Configure RTS/CTS only when hardware flow control is enabled */ + if (cfg->uart_proto_cfg.flow_ctrl & UART_HW_FLOWCTRL_RTS) { + ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_RTS_PIN_IDX); + } + if (cfg->uart_proto_cfg.flow_ctrl & UART_HW_FLOWCTRL_CTS) { + ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_CTS_PIN_IDX); + } return ret; }