feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets

Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3 and ESP32-P4 to
expose the number of FSLS USB_WRAP PHYs available on each target. This
separates FSLS USB_WRAP support from OTG/UTMI support so that downstream
code can gate FSLS PHY handling independently.
This commit is contained in:
igor.masar
2026-09-04 09:38:35 +08:00
committed by morris
parent 52540e376d
commit ee4f1deb85
6 changed files with 15 additions and 0 deletions
@@ -1359,6 +1359,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 2
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_USB_UTMI_PHY_NUM
int
default 1
@@ -483,6 +483,7 @@
// USB OTG Caps
#define SOC_USB_OTG_PERIPH_NUM (2U)
#define SOC_USB_FSLS_PHY_NUM (1U)
// USB PHY Caps
#define SOC_USB_UTMI_PHY_NUM (1U)
@@ -911,6 +911,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
@@ -380,6 +380,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
@@ -1111,6 +1111,10 @@ config SOC_USB_OTG_PERIPH_NUM
int
default 1
config SOC_USB_FSLS_PHY_NUM
int
default 1
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
@@ -428,6 +428,7 @@
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
#define SOC_USB_FSLS_PHY_NUM (1U)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,