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feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3 and ESP32-P4 to expose the number of FSLS USB_WRAP PHYs available on each target. This separates FSLS USB_WRAP support from OTG/UTMI support so that downstream code can gate FSLS PHY handling independently.
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@@ -1359,6 +1359,10 @@ config SOC_USB_OTG_PERIPH_NUM
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int
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default 2
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config SOC_USB_FSLS_PHY_NUM
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int
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default 1
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config SOC_USB_UTMI_PHY_NUM
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int
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default 1
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@@ -483,6 +483,7 @@
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// USB OTG Caps
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#define SOC_USB_OTG_PERIPH_NUM (2U)
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#define SOC_USB_FSLS_PHY_NUM (1U)
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// USB PHY Caps
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#define SOC_USB_UTMI_PHY_NUM (1U)
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@@ -911,6 +911,10 @@ config SOC_USB_OTG_PERIPH_NUM
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int
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default 1
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config SOC_USB_FSLS_PHY_NUM
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int
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default 1
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config SOC_SHA_DMA_MAX_BUFFER_SIZE
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int
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default 3968
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@@ -380,6 +380,7 @@
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/*-------------------------- USB CAPS ----------------------------------------*/
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#define SOC_USB_OTG_PERIPH_NUM (1U)
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#define SOC_USB_FSLS_PHY_NUM (1U)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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@@ -1111,6 +1111,10 @@ config SOC_USB_OTG_PERIPH_NUM
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int
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default 1
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config SOC_USB_FSLS_PHY_NUM
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int
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default 1
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config SOC_SHA_DMA_MAX_BUFFER_SIZE
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int
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default 3968
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@@ -428,6 +428,7 @@
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/*-------------------------- USB CAPS ----------------------------------------*/
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#define SOC_USB_OTG_PERIPH_NUM (1U)
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#define SOC_USB_FSLS_PHY_NUM (1U)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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